1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __ASM_ARCH_DMA_H 3*4882a593Smuzhiyun #define __ASM_ARCH_DMA_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/types.h> 6*4882a593Smuzhiyun #include <linux/dmaengine.h> 7*4882a593Smuzhiyun #include <linux/dma-mapping.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* 10*4882a593Smuzhiyun * M2P channels. 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Note that these values are also directly used for setting the PPALLOC 13*4882a593Smuzhiyun * register. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define EP93XX_DMA_I2S1 0 16*4882a593Smuzhiyun #define EP93XX_DMA_I2S2 1 17*4882a593Smuzhiyun #define EP93XX_DMA_AAC1 2 18*4882a593Smuzhiyun #define EP93XX_DMA_AAC2 3 19*4882a593Smuzhiyun #define EP93XX_DMA_AAC3 4 20*4882a593Smuzhiyun #define EP93XX_DMA_I2S3 5 21*4882a593Smuzhiyun #define EP93XX_DMA_UART1 6 22*4882a593Smuzhiyun #define EP93XX_DMA_UART2 7 23*4882a593Smuzhiyun #define EP93XX_DMA_UART3 8 24*4882a593Smuzhiyun #define EP93XX_DMA_IRDA 9 25*4882a593Smuzhiyun /* M2M channels */ 26*4882a593Smuzhiyun #define EP93XX_DMA_SSP 10 27*4882a593Smuzhiyun #define EP93XX_DMA_IDE 11 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /** 30*4882a593Smuzhiyun * struct ep93xx_dma_data - configuration data for the EP93xx dmaengine 31*4882a593Smuzhiyun * @port: peripheral which is requesting the channel 32*4882a593Smuzhiyun * @direction: TX/RX channel 33*4882a593Smuzhiyun * @name: optional name for the channel, this is displayed in /proc/interrupts 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * This information is passed as private channel parameter in a filter 36*4882a593Smuzhiyun * function. Note that this is only needed for slave/cyclic channels. For 37*4882a593Smuzhiyun * memcpy channels %NULL data should be passed. 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun struct ep93xx_dma_data { 40*4882a593Smuzhiyun int port; 41*4882a593Smuzhiyun enum dma_transfer_direction direction; 42*4882a593Smuzhiyun const char *name; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /** 46*4882a593Smuzhiyun * struct ep93xx_dma_chan_data - platform specific data for a DMA channel 47*4882a593Smuzhiyun * @name: name of the channel, used for getting the right clock for the channel 48*4882a593Smuzhiyun * @base: mapped registers 49*4882a593Smuzhiyun * @irq: interrupt number used by this channel 50*4882a593Smuzhiyun */ 51*4882a593Smuzhiyun struct ep93xx_dma_chan_data { 52*4882a593Smuzhiyun const char *name; 53*4882a593Smuzhiyun void __iomem *base; 54*4882a593Smuzhiyun int irq; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /** 58*4882a593Smuzhiyun * struct ep93xx_dma_platform_data - platform data for the dmaengine driver 59*4882a593Smuzhiyun * @channels: array of channels which are passed to the driver 60*4882a593Smuzhiyun * @num_channels: number of channels in the array 61*4882a593Smuzhiyun * 62*4882a593Smuzhiyun * This structure is passed to the DMA engine driver via platform data. For 63*4882a593Smuzhiyun * M2P channels, contract is that even channels are for TX and odd for RX. 64*4882a593Smuzhiyun * There is no requirement for the M2M channels. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun struct ep93xx_dma_platform_data { 67*4882a593Smuzhiyun struct ep93xx_dma_chan_data *channels; 68*4882a593Smuzhiyun size_t num_channels; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun ep93xx_dma_chan_is_m2p(struct dma_chan * chan)71*4882a593Smuzhiyunstatic inline bool ep93xx_dma_chan_is_m2p(struct dma_chan *chan) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun return !strcmp(dev_name(chan->device->dev), "ep93xx-dma-m2p"); 74*4882a593Smuzhiyun } 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /** 77*4882a593Smuzhiyun * ep93xx_dma_chan_direction - returns direction the channel can be used 78*4882a593Smuzhiyun * @chan: channel 79*4882a593Smuzhiyun * 80*4882a593Smuzhiyun * This function can be used in filter functions to find out whether the 81*4882a593Smuzhiyun * channel supports given DMA direction. Only M2P channels have such 82*4882a593Smuzhiyun * limitation, for M2M channels the direction is configurable. 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun static inline enum dma_transfer_direction ep93xx_dma_chan_direction(struct dma_chan * chan)85*4882a593Smuzhiyunep93xx_dma_chan_direction(struct dma_chan *chan) 86*4882a593Smuzhiyun { 87*4882a593Smuzhiyun if (!ep93xx_dma_chan_is_m2p(chan)) 88*4882a593Smuzhiyun return DMA_TRANS_NONE; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* even channels are for TX, odd for RX */ 91*4882a593Smuzhiyun return (chan->chan_id % 2 == 0) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 92*4882a593Smuzhiyun } 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #endif /* __ASM_ARCH_DMA_H */ 95