1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/owl-dma.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Actions Semi Owl SoCs DMA controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun The OWL DMA is a general-purpose direct memory access controller capable of 11*4882a593Smuzhiyun supporting 10 and 12 independent DMA channels for S700 and S900 SoCs 12*4882a593Smuzhiyun respectively. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunmaintainers: 15*4882a593Smuzhiyun - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunallOf: 18*4882a593Smuzhiyun - $ref: "dma-controller.yaml#" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun enum: 23*4882a593Smuzhiyun - actions,s900-dma 24*4882a593Smuzhiyun - actions,s700-dma 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reg: 27*4882a593Smuzhiyun maxItems: 1 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun interrupts: 30*4882a593Smuzhiyun description: 31*4882a593Smuzhiyun controller supports 4 interrupts, which are freely assignable to the 32*4882a593Smuzhiyun DMA channels. 33*4882a593Smuzhiyun maxItems: 4 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun "#dma-cells": 36*4882a593Smuzhiyun const: 1 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun dma-channels: 39*4882a593Smuzhiyun maximum: 12 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun dma-requests: 42*4882a593Smuzhiyun maximum: 46 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun clocks: 45*4882a593Smuzhiyun maxItems: 1 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun Phandle and Specifier of the clock feeding the DMA controller. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun power-domains: 50*4882a593Smuzhiyun maxItems: 1 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunrequired: 53*4882a593Smuzhiyun - compatible 54*4882a593Smuzhiyun - reg 55*4882a593Smuzhiyun - interrupts 56*4882a593Smuzhiyun - "#dma-cells" 57*4882a593Smuzhiyun - dma-channels 58*4882a593Smuzhiyun - dma-requests 59*4882a593Smuzhiyun - clocks 60*4882a593Smuzhiyun 61*4882a593SmuzhiyununevaluatedProperties: false 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunexamples: 64*4882a593Smuzhiyun - | 65*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 66*4882a593Smuzhiyun dma: dma-controller@e0260000 { 67*4882a593Smuzhiyun compatible = "actions,s900-dma"; 68*4882a593Smuzhiyun reg = <0xe0260000 0x1000>; 69*4882a593Smuzhiyun interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 70*4882a593Smuzhiyun <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 71*4882a593Smuzhiyun <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 72*4882a593Smuzhiyun <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 73*4882a593Smuzhiyun #dma-cells = <1>; 74*4882a593Smuzhiyun dma-channels = <12>; 75*4882a593Smuzhiyun dma-requests = <46>; 76*4882a593Smuzhiyun clocks = <&clock 22>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun... 80