1*4882a593SmuzhiyunNXP Layerscape SoC qDMA Controller 2*4882a593Smuzhiyun================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis device follows the generic DMA bindings defined in dma/dma.txt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: Must be one of 9*4882a593Smuzhiyun "fsl,ls1021a-qdma": for LS1021A Board 10*4882a593Smuzhiyun "fsl,ls1028a-qdma": for LS1028A Board 11*4882a593Smuzhiyun "fsl,ls1043a-qdma": for ls1043A Board 12*4882a593Smuzhiyun "fsl,ls1046a-qdma": for ls1046A Board 13*4882a593Smuzhiyun- reg: Should contain the register's base address and length. 14*4882a593Smuzhiyun- interrupts: Should contain a reference to the interrupt used by this 15*4882a593Smuzhiyun device. 16*4882a593Smuzhiyun- interrupt-names: Should contain interrupt names: 17*4882a593Smuzhiyun "qdma-queue0": the block0 interrupt 18*4882a593Smuzhiyun "qdma-queue1": the block1 interrupt 19*4882a593Smuzhiyun "qdma-queue2": the block2 interrupt 20*4882a593Smuzhiyun "qdma-queue3": the block3 interrupt 21*4882a593Smuzhiyun "qdma-error": the error interrupt 22*4882a593Smuzhiyun- fsl,dma-queues: Should contain number of queues supported. 23*4882a593Smuzhiyun- dma-channels: Number of DMA channels supported 24*4882a593Smuzhiyun- block-number: the virtual block number 25*4882a593Smuzhiyun- block-offset: the offset of different virtual block 26*4882a593Smuzhiyun- status-sizes: status queue size of per virtual block 27*4882a593Smuzhiyun- queue-sizes: command queue size of per virtual block, the size number 28*4882a593Smuzhiyun based on queues 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunOptional properties: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- dma-channels: Number of DMA channels supported by the controller. 33*4882a593Smuzhiyun- big-endian: If present registers and hardware scatter/gather descriptors 34*4882a593Smuzhiyun of the qDMA are implemented in big endian mode, otherwise in little 35*4882a593Smuzhiyun mode. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExamples: 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun qdma: dma-controller@8390000 { 40*4882a593Smuzhiyun compatible = "fsl,ls1021a-qdma"; 41*4882a593Smuzhiyun reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */ 42*4882a593Smuzhiyun <0x0 0x8389000 0x0 0x1000>, /* Status regs */ 43*4882a593Smuzhiyun <0x0 0x838a000 0x0 0x2000>; /* Block regs */ 44*4882a593Smuzhiyun interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 45*4882a593Smuzhiyun <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 46*4882a593Smuzhiyun <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 47*4882a593Smuzhiyun interrupt-names = "qdma-error", 48*4882a593Smuzhiyun "qdma-queue0", "qdma-queue1"; 49*4882a593Smuzhiyun dma-channels = <8>; 50*4882a593Smuzhiyun block-number = <2>; 51*4882a593Smuzhiyun block-offset = <0x1000>; 52*4882a593Smuzhiyun fsl,dma-queues = <2>; 53*4882a593Smuzhiyun status-sizes = <64>; 54*4882a593Smuzhiyun queue-sizes = <64 64>; 55*4882a593Smuzhiyun big-endian; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593SmuzhiyunDMA clients must use the format described in dma/dma.txt file. 59