1*4882a593Smuzhiyun* Freescale MXS DMA 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Should be "fsl,<chip>-dma-apbh" or "fsl,<chip>-dma-apbx" 5*4882a593Smuzhiyun- reg : Should contain registers location and length 6*4882a593Smuzhiyun- interrupts : Should contain the interrupt numbers of DMA channels. 7*4882a593Smuzhiyun If a channel is empty/reserved, 0 should be filled in place. 8*4882a593Smuzhiyun- #dma-cells : Must be <1>. The number cell specifies the channel ID. 9*4882a593Smuzhiyun- dma-channels : Number of channels supported by the DMA controller 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunOptional properties: 12*4882a593Smuzhiyun- interrupt-names : Name of DMA channel interrupts 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunSupported chips: 15*4882a593Smuzhiyunimx23, imx28. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExamples: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyundma_apbh: dma-apbh@80004000 { 20*4882a593Smuzhiyun compatible = "fsl,imx28-dma-apbh"; 21*4882a593Smuzhiyun reg = <0x80004000 0x2000>; 22*4882a593Smuzhiyun interrupts = <82 83 84 85 23*4882a593Smuzhiyun 88 88 88 88 24*4882a593Smuzhiyun 88 88 88 88 25*4882a593Smuzhiyun 87 86 0 0>; 26*4882a593Smuzhiyun interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", 27*4882a593Smuzhiyun "gpmi0", "gmpi1", "gpmi2", "gmpi3", 28*4882a593Smuzhiyun "gpmi4", "gmpi5", "gpmi6", "gmpi7", 29*4882a593Smuzhiyun "hsadc", "lcdif", "empty", "empty"; 30*4882a593Smuzhiyun #dma-cells = <1>; 31*4882a593Smuzhiyun dma-channels = <16>; 32*4882a593Smuzhiyun}; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyundma_apbx: dma-apbx@80024000 { 35*4882a593Smuzhiyun compatible = "fsl,imx28-dma-apbx"; 36*4882a593Smuzhiyun reg = <0x80024000 0x2000>; 37*4882a593Smuzhiyun interrupts = <78 79 66 0 38*4882a593Smuzhiyun 80 81 68 69 39*4882a593Smuzhiyun 70 71 72 73 40*4882a593Smuzhiyun 74 75 76 77>; 41*4882a593Smuzhiyun interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", 42*4882a593Smuzhiyun "saif0", "saif1", "i2c0", "i2c1", 43*4882a593Smuzhiyun "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", 44*4882a593Smuzhiyun "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; 45*4882a593Smuzhiyun #dma-cells = <1>; 46*4882a593Smuzhiyun dma-channels = <16>; 47*4882a593Smuzhiyun}; 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunDMA clients connected to the MXS DMA controller must use the format 50*4882a593Smuzhiyundescribed in the dma.txt file. 51*4882a593Smuzhiyun 52*4882a593SmuzhiyunExamples: 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunauart0: serial@8006a000 { 55*4882a593Smuzhiyun compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 56*4882a593Smuzhiyun reg = <0x8006a000 0x2000>; 57*4882a593Smuzhiyun interrupts = <112>; 58*4882a593Smuzhiyun dmas = <&dma_apbx 8>, <&dma_apbx 9>; 59*4882a593Smuzhiyun dma-names = "rx", "tx"; 60*4882a593Smuzhiyun}; 61