xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/st_fdma.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* STMicroelectronics Flexible Direct Memory Access Device Tree bindings
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe FDMA is a general-purpose direct memory access controller capable of
4*4882a593Smuzhiyunsupporting 16 independent DMA channels. It accepts up to 32 DMA requests.
5*4882a593SmuzhiyunThe FDMA is based on a Slim processor which requires a firmware.
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun* FDMA Controller
8*4882a593Smuzhiyun
9*4882a593SmuzhiyunRequired properties:
10*4882a593Smuzhiyun- compatible	: Should be one of
11*4882a593Smuzhiyun		 - st,stih407-fdma-mpe31-11, "st,slim-rproc";
12*4882a593Smuzhiyun		 - st,stih407-fdma-mpe31-12, "st,slim-rproc";
13*4882a593Smuzhiyun		 - st,stih407-fdma-mpe31-13, "st,slim-rproc";
14*4882a593Smuzhiyun- reg		: Should contain an entry for each name in reg-names
15*4882a593Smuzhiyun- reg-names	: Must contain "slimcore", "dmem", "peripherals", "imem" entries
16*4882a593Smuzhiyun- interrupts	: Should contain one interrupt shared by all channels
17*4882a593Smuzhiyun- dma-channels	: Number of channels supported by the controller
18*4882a593Smuzhiyun- #dma-cells	: Must be <3>. See DMA client section below
19*4882a593Smuzhiyun- clocks	: Must contain an entry for each clock
20*4882a593SmuzhiyunSee: Documentation/devicetree/bindings/clock/clock-bindings.txt
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunExample:
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	fdma0: dma-controller@8e20000 {
26*4882a593Smuzhiyun		compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
27*4882a593Smuzhiyun		reg = <0x8e20000 0x8000>,
28*4882a593Smuzhiyun		      <0x8e30000 0x3000>,
29*4882a593Smuzhiyun		      <0x8e37000 0x1000>,
30*4882a593Smuzhiyun		      <0x8e38000 0x8000>;
31*4882a593Smuzhiyun		reg-names = "slimcore", "dmem", "peripherals", "imem";
32*4882a593Smuzhiyun		clocks = <&clk_s_c0_flexgen CLK_FDMA>,
33*4882a593Smuzhiyun			 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
34*4882a593Smuzhiyun			 <&clk_s_c0_flexgen CLK_EXT2F_A9>,
35*4882a593Smuzhiyun			 <&clk_s_c0_flexgen CLK_EXT2F_A9>;
36*4882a593Smuzhiyun		interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
37*4882a593Smuzhiyun		dma-channels = <16>;
38*4882a593Smuzhiyun		#dma-cells = <3>;
39*4882a593Smuzhiyun	};
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun* DMA client
42*4882a593Smuzhiyun
43*4882a593SmuzhiyunRequired properties:
44*4882a593Smuzhiyun- dmas: Comma separated list of dma channel requests
45*4882a593Smuzhiyun- dma-names: Names of the aforementioned requested channels
46*4882a593Smuzhiyun
47*4882a593SmuzhiyunEach dmas request consists of 4 cells:
48*4882a593Smuzhiyun1. A phandle pointing to the FDMA controller
49*4882a593Smuzhiyun2. The request line number
50*4882a593Smuzhiyun3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h)
51*4882a593Smuzhiyun -bit 2-0: Holdoff value, dreq will be masked for
52*4882a593Smuzhiyun	0x0: 0-0.5us
53*4882a593Smuzhiyun	0x1: 0.5-1us
54*4882a593Smuzhiyun	0x2: 1-1.5us
55*4882a593Smuzhiyun -bit 17: data swap
56*4882a593Smuzhiyun	0x0: disabled
57*4882a593Smuzhiyun	0x1: enabled
58*4882a593Smuzhiyun -bit 21: Increment Address
59*4882a593Smuzhiyun	0x0: no address increment between transfers
60*4882a593Smuzhiyun	0x1: increment address between transfers
61*4882a593Smuzhiyun -bit 22: 2 STBus Initiator Coprocessor interface
62*4882a593Smuzhiyun	0x0: high priority port
63*4882a593Smuzhiyun	0x1: low priority port
64*4882a593Smuzhiyun4. transfers type
65*4882a593Smuzhiyun 0 free running
66*4882a593Smuzhiyun 1 paced
67*4882a593Smuzhiyun
68*4882a593SmuzhiyunExample:
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun	sti_uni_player2: sti-uni-player@2 {
71*4882a593Smuzhiyun		compatible = "st,sti-uni-player";
72*4882a593Smuzhiyun		#sound-dai-cells = <0>;
73*4882a593Smuzhiyun		st,syscfg = <&syscfg_core>;
74*4882a593Smuzhiyun		clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
75*4882a593Smuzhiyun		assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
76*4882a593Smuzhiyun		assigned-clock-parents = <&clk_s_d0_quadfs 2>;
77*4882a593Smuzhiyun		assigned-clock-rates = <50000000>;
78*4882a593Smuzhiyun		reg = <0x8D82000 0x158>;
79*4882a593Smuzhiyun		interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
80*4882a593Smuzhiyun		dmas = <&fdma0 4 0 1>;
81*4882a593Smuzhiyun		dai-name = "Uni Player #1 (DAC)";
82*4882a593Smuzhiyun		dma-names = "tx";
83*4882a593Smuzhiyun		st,uniperiph-id = <2>;
84*4882a593Smuzhiyun		st,version = <5>;
85*4882a593Smuzhiyun		st,mode = "PCM";
86*4882a593Smuzhiyun	};
87