1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * arch/arm/mach-ep93xx/dma.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Platform support code for the EP93xx dmaengine driver.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (C) 2011 Mika Westerberg
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This work is based on the original dma-m2p implementation with
10*4882a593Smuzhiyun * following copyrights:
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
13*4882a593Smuzhiyun * Copyright (C) 2006 Applied Data Systems
14*4882a593Smuzhiyun * Copyright (C) 2009 Ryan Mallon <rmallon@gmail.com>
15*4882a593Smuzhiyun */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <linux/dmaengine.h>
18*4882a593Smuzhiyun #include <linux/dma-mapping.h>
19*4882a593Smuzhiyun #include <linux/init.h>
20*4882a593Smuzhiyun #include <linux/interrupt.h>
21*4882a593Smuzhiyun #include <linux/kernel.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <linux/platform_data/dma-ep93xx.h>
25*4882a593Smuzhiyun #include "hardware.h"
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "soc.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define DMA_CHANNEL(_name, _base, _irq) \
30*4882a593Smuzhiyun { .name = (_name), .base = (_base), .irq = (_irq) }
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * DMA M2P channels.
34*4882a593Smuzhiyun *
35*4882a593Smuzhiyun * On the EP93xx chip the following peripherals my be allocated to the 10
36*4882a593Smuzhiyun * Memory to Internal Peripheral (M2P) channels (5 transmit + 5 receive).
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun * I2S contains 3 Tx and 3 Rx DMA Channels
39*4882a593Smuzhiyun * AAC contains 3 Tx and 3 Rx DMA Channels
40*4882a593Smuzhiyun * UART1 contains 1 Tx and 1 Rx DMA Channels
41*4882a593Smuzhiyun * UART2 contains 1 Tx and 1 Rx DMA Channels
42*4882a593Smuzhiyun * UART3 contains 1 Tx and 1 Rx DMA Channels
43*4882a593Smuzhiyun * IrDA contains 1 Tx and 1 Rx DMA Channels
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * Registers are mapped statically in ep93xx_map_io().
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun static struct ep93xx_dma_chan_data ep93xx_dma_m2p_channels[] = {
48*4882a593Smuzhiyun DMA_CHANNEL("m2p0", EP93XX_DMA_BASE + 0x0000, IRQ_EP93XX_DMAM2P0),
49*4882a593Smuzhiyun DMA_CHANNEL("m2p1", EP93XX_DMA_BASE + 0x0040, IRQ_EP93XX_DMAM2P1),
50*4882a593Smuzhiyun DMA_CHANNEL("m2p2", EP93XX_DMA_BASE + 0x0080, IRQ_EP93XX_DMAM2P2),
51*4882a593Smuzhiyun DMA_CHANNEL("m2p3", EP93XX_DMA_BASE + 0x00c0, IRQ_EP93XX_DMAM2P3),
52*4882a593Smuzhiyun DMA_CHANNEL("m2p4", EP93XX_DMA_BASE + 0x0240, IRQ_EP93XX_DMAM2P4),
53*4882a593Smuzhiyun DMA_CHANNEL("m2p5", EP93XX_DMA_BASE + 0x0200, IRQ_EP93XX_DMAM2P5),
54*4882a593Smuzhiyun DMA_CHANNEL("m2p6", EP93XX_DMA_BASE + 0x02c0, IRQ_EP93XX_DMAM2P6),
55*4882a593Smuzhiyun DMA_CHANNEL("m2p7", EP93XX_DMA_BASE + 0x0280, IRQ_EP93XX_DMAM2P7),
56*4882a593Smuzhiyun DMA_CHANNEL("m2p8", EP93XX_DMA_BASE + 0x0340, IRQ_EP93XX_DMAM2P8),
57*4882a593Smuzhiyun DMA_CHANNEL("m2p9", EP93XX_DMA_BASE + 0x0300, IRQ_EP93XX_DMAM2P9),
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static struct ep93xx_dma_platform_data ep93xx_dma_m2p_data = {
61*4882a593Smuzhiyun .channels = ep93xx_dma_m2p_channels,
62*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(ep93xx_dma_m2p_channels),
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static u64 ep93xx_dma_m2p_mask = DMA_BIT_MASK(32);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static struct platform_device ep93xx_dma_m2p_device = {
68*4882a593Smuzhiyun .name = "ep93xx-dma-m2p",
69*4882a593Smuzhiyun .id = -1,
70*4882a593Smuzhiyun .dev = {
71*4882a593Smuzhiyun .platform_data = &ep93xx_dma_m2p_data,
72*4882a593Smuzhiyun .dma_mask = &ep93xx_dma_m2p_mask,
73*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * DMA M2M channels.
79*4882a593Smuzhiyun *
80*4882a593Smuzhiyun * There are 2 M2M channels which support memcpy/memset and in addition simple
81*4882a593Smuzhiyun * hardware requests from/to SSP and IDE. We do not implement an external
82*4882a593Smuzhiyun * hardware requests.
83*4882a593Smuzhiyun *
84*4882a593Smuzhiyun * Registers are mapped statically in ep93xx_map_io().
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun static struct ep93xx_dma_chan_data ep93xx_dma_m2m_channels[] = {
87*4882a593Smuzhiyun DMA_CHANNEL("m2m0", EP93XX_DMA_BASE + 0x0100, IRQ_EP93XX_DMAM2M0),
88*4882a593Smuzhiyun DMA_CHANNEL("m2m1", EP93XX_DMA_BASE + 0x0140, IRQ_EP93XX_DMAM2M1),
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun static struct ep93xx_dma_platform_data ep93xx_dma_m2m_data = {
92*4882a593Smuzhiyun .channels = ep93xx_dma_m2m_channels,
93*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(ep93xx_dma_m2m_channels),
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static u64 ep93xx_dma_m2m_mask = DMA_BIT_MASK(32);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun static struct platform_device ep93xx_dma_m2m_device = {
99*4882a593Smuzhiyun .name = "ep93xx-dma-m2m",
100*4882a593Smuzhiyun .id = -1,
101*4882a593Smuzhiyun .dev = {
102*4882a593Smuzhiyun .platform_data = &ep93xx_dma_m2m_data,
103*4882a593Smuzhiyun .dma_mask = &ep93xx_dma_m2m_mask,
104*4882a593Smuzhiyun .coherent_dma_mask = DMA_BIT_MASK(32),
105*4882a593Smuzhiyun },
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
ep93xx_dma_init(void)108*4882a593Smuzhiyun static int __init ep93xx_dma_init(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun platform_device_register(&ep93xx_dma_m2p_device);
111*4882a593Smuzhiyun platform_device_register(&ep93xx_dma_m2m_device);
112*4882a593Smuzhiyun return 0;
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun arch_initcall(ep93xx_dma_init);
115