1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dma/dma-common.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: DMA Engine Generic Binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Vinod Koul <vkoul@kernel.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun Generic binding to provide a way for a driver using DMA Engine to 14*4882a593Smuzhiyun retrieve the DMA request or channel information that goes from a 15*4882a593Smuzhiyun hardware device to a DMA controller. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunselect: false 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun "#dma-cells": 21*4882a593Smuzhiyun minimum: 1 22*4882a593Smuzhiyun # Should be enough 23*4882a593Smuzhiyun maximum: 255 24*4882a593Smuzhiyun description: 25*4882a593Smuzhiyun Used to provide DMA controller specific information. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun dma-channel-mask: 28*4882a593Smuzhiyun description: 29*4882a593Smuzhiyun Bitmask of available DMA channels in ascending order that are 30*4882a593Smuzhiyun not reserved by firmware and are available to the 31*4882a593Smuzhiyun kernel. i.e. first channel corresponds to LSB. 32*4882a593Smuzhiyun The first item in the array is for channels 0-31, the second is for 33*4882a593Smuzhiyun channels 32-63, etc. 34*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32-array 35*4882a593Smuzhiyun items: 36*4882a593Smuzhiyun minItems: 1 37*4882a593Smuzhiyun # Should be enough 38*4882a593Smuzhiyun maxItems: 255 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun dma-channels: 41*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 42*4882a593Smuzhiyun description: 43*4882a593Smuzhiyun Number of DMA channels supported by the controller. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun dma-requests: 46*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 47*4882a593Smuzhiyun description: 48*4882a593Smuzhiyun Number of DMA request signals supported by the controller. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunrequired: 51*4882a593Smuzhiyun - "#dma-cells" 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunadditionalProperties: true 54