| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/ |
| H A D | sdhci-st.txt | 57 - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
109 sd-uhs-ddr50;
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| H A D | sdhci-omap.txt | 15 "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104",
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| H A D | cdns,sdhci.yaml | 67 cdns,phy-input-delay-sd-uhs-ddr50:
68 description: Value of the delay in the input path for SD UHS DDR50 timing
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| H A D | mmc-controller.yaml | 151 sd-uhs-ddr50:
154 SD UHS DDR50 speed is supported.
339 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$":
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| H A D | sdhci-am654.yaml | 93 ti,otap-del-sel-ddr50:
94 description: Output tap delay for SD UHS DDR50 timing
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| H A D | brcm,sdhci-brcmstb.txt | 22 sd-uhs-ddr50;
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| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/misc/ |
| H A D | intel,baytrail-fsp.txt | 38 - fsp,emmc45-ddr50-enabled
131 fsp,emmc45-ddr50-enabled;
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| /OK3568_Linux_fs/kernel/arch/arm/boot/dts/ |
| H A D | stih410-b2120.dts | 34 sd-uhs-ddr50;
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| H A D | stih418-b2199.dts | 84 sd-uhs-ddr50;
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| H A D | dra72-evm.dts | 94 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra72-evm-revc.dts | 124 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| H A D | dra7-evm.dts | 389 …pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50"…
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| H A D | dra71-evm.dts | 201 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
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| /OK3568_Linux_fs/u-boot/board/rockchip/evb_rk3328/ |
| H A D | README | 8 * eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
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| /OK3568_Linux_fs/kernel/drivers/mmc/host/ |
| H A D | dw_mmc-k3.c | 84 {0}, /* 7: DDR50 */
96 {0}, /* 7: DDR50 */
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| H A D | sdhci-pxav3.c | 140 * According to erratum 'FE-2946959' both SDR50 and DDR50 in armada_38x_quirks()
147 …dev_warn(&pdev->dev, "conf-sdio3 register not found: disabling SDR50 and DDR50 modes.\nConsider up… in armada_38x_quirks()
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| H A D | sdhci-of-sparx5.c | 154 SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
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| /OK3568_Linux_fs/u-boot/drivers/mmc/ |
| H A D | sdhci-cadence.c | 60 { "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
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| /OK3568_Linux_fs/u-boot/board/rockchip/evb_rk3399/ |
| H A D | README | 10 * eMMC: support eMMC 5.0/5.1, suport HS400, HS200, DDR50
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| /OK3568_Linux_fs/kernel/drivers/mmc/core/ |
| H A D | debugfs.c | 141 str = "sd uhs DDR50"; in mmc_ios_show()
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| H A D | sd.c | 548 * Current limit switch is only defined for SDR50, SDR104, and DDR50 in sd_set_current_limit()
663 * tuning is also available for DDR50 mode. in mmc_sd_init_uhs_card()
666 pr_warn("%s: ddr50 tuning failed\n", in mmc_sd_init_uhs_card()
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| /OK3568_Linux_fs/kernel/arch/arm64/boot/dts/amlogic/ |
| H A D | meson-gxl-s905x-libretech-cc-v2.dts | 255 sd-uhs-ddr50;
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| H A D | meson-gxbb-nanopi-k2.dts | 309 sd-uhs-ddr50;
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| /OK3568_Linux_fs/u-boot/include/ |
| H A D | mvebu_mmc.h | 253 /* Host supports UHS DDR50 mode */
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| /OK3568_Linux_fs/u-boot/arch/x86/dts/ |
| H A D | bayleybay.dts | 269 fsp,emmc45-ddr50-enabled;
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