1*4882a593Smuzhiyun* STMicroelectronics sdhci-st MMC/SD controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis file documents the differences between the core properties in 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/mmc/mmc.txt and the properties 5*4882a593Smuzhiyunused by the sdhci-st driver. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407" 9*4882a593Smuzhiyun to set the internal glue logic used for configuring the MMC 10*4882a593Smuzhiyun subsystem (mmcss) inside the FlashSS (available in STiH407 SoC 11*4882a593Smuzhiyun family). 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory) 14*4882a593Smuzhiyun See: Documentation/devicetree/bindings/resource-names.txt 15*4882a593Smuzhiyun- clocks: Phandle to the clock. 16*4882a593Smuzhiyun See: Documentation/devicetree/bindings/clock/clock-bindings.txt 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- interrupts: One mmc interrupt should be described here. 19*4882a593Smuzhiyun- interrupt-names: Should be "mmcirq". 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- pinctrl-names: A pinctrl state names "default" must be defined. 22*4882a593Smuzhiyun- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller. 23*4882a593Smuzhiyun See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- reg: This must provide the host controller base address and it can also 26*4882a593Smuzhiyun contain the FlashSS Top register for TX/RX delay used by the driver 27*4882a593Smuzhiyun to configure DLL inside the flashSS, if so reg-names must also be 28*4882a593Smuzhiyun specified. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunOptional properties: 31*4882a593Smuzhiyun- reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional 32*4882a593Smuzhiyun for eMMC on stih407 family silicon to configure DLL inside FlashSS. 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun- non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC 35*4882a593Smuzhiyun family. 36*4882a593Smuzhiyun See: Documentation/devicetree/bindings/mmc/mmc.txt. 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun- bus-width: Number of data lines. 39*4882a593Smuzhiyun See: Documentation/devicetree/bindings/mmc/mmc.txt. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for 42*4882a593Smuzhiyun configuring the CCONFIG3 in the mmcss. 43*4882a593Smuzhiyun See: Documentation/devicetree/bindings/mmc/mmc.txt. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun- resets: Phandle and reset specifier pair to softreset line of HC IP. 46*4882a593Smuzhiyun See: Documentation/devicetree/bindings/reset/reset.txt 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun- vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd 49*4882a593Smuzhiyun supply in eMMC/SD specs. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun- sd-uhs-sdr50: To enable the SDR50 in the mmcss. 52*4882a593Smuzhiyun See: Documentation/devicetree/bindings/mmc/mmc.txt. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun- sd-uhs-sdr104: To enable the SDR104 in the mmcss. 55*4882a593Smuzhiyun See: Documentation/devicetree/bindings/mmc/mmc.txt. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun- sd-uhs-ddr50: To enable the DDR50 in the mmcss. 58*4882a593Smuzhiyun See: Documentation/devicetree/bindings/mmc/mmc.txt. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunExample: 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun/* Example stih416e eMMC configuration */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunmmc0: sdhci@fe81e000 { 65*4882a593Smuzhiyun compatible = "st,sdhci"; 66*4882a593Smuzhiyun reg = <0xfe81e000 0x1000>; 67*4882a593Smuzhiyun interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>; 68*4882a593Smuzhiyun interrupt-names = "mmcirq"; 69*4882a593Smuzhiyun pinctrl-names = "default"; 70*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_mmc0>; 71*4882a593Smuzhiyun clock-names = "mmc"; 72*4882a593Smuzhiyun clocks = <&clk_s_a1_ls 1>; 73*4882a593Smuzhiyun bus-width = <8> 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun/* Example SD stih407 family configuration */ 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunmmc1: sdhci@9080000 { 78*4882a593Smuzhiyun compatible = "st,sdhci-stih407", "st,sdhci"; 79*4882a593Smuzhiyun reg = <0x09080000 0x7ff>; 80*4882a593Smuzhiyun reg-names = "mmc"; 81*4882a593Smuzhiyun interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; 82*4882a593Smuzhiyun interrupt-names = "mmcirq"; 83*4882a593Smuzhiyun pinctrl-names = "default"; 84*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_sd1>; 85*4882a593Smuzhiyun clock-names = "mmc"; 86*4882a593Smuzhiyun clocks = <&clk_s_c0_flexgen CLK_MMC_1>; 87*4882a593Smuzhiyun resets = <&softreset STIH407_MMC1_SOFTRESET>; 88*4882a593Smuzhiyun bus-width = <4>; 89*4882a593Smuzhiyun}; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun/* Example eMMC stih407 family configuration */ 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunmmc0: sdhci@9060000 { 94*4882a593Smuzhiyun compatible = "st,sdhci-stih407", "st,sdhci"; 95*4882a593Smuzhiyun reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 96*4882a593Smuzhiyun reg-names = "mmc", "top-mmc-delay"; 97*4882a593Smuzhiyun interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; 98*4882a593Smuzhiyun interrupt-names = "mmcirq"; 99*4882a593Smuzhiyun pinctrl-names = "default"; 100*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_mmc0>; 101*4882a593Smuzhiyun clock-names = "mmc"; 102*4882a593Smuzhiyun clocks = <&clk_s_c0_flexgen CLK_MMC_0>; 103*4882a593Smuzhiyun vqmmc-supply = <&vmmc_reg>; 104*4882a593Smuzhiyun max-frequency = <200000000>; 105*4882a593Smuzhiyun bus-width = <8>; 106*4882a593Smuzhiyun non-removable; 107*4882a593Smuzhiyun sd-uhs-sdr50; 108*4882a593Smuzhiyun sd-uhs-sdr104; 109*4882a593Smuzhiyun sd-uhs-ddr50; 110*4882a593Smuzhiyun}; 111