Home
last modified time | relevance | path

Searched +full:data +full:- +full:shift (Results 1 – 25 of 1052) sorted by relevance

12345678910>>...43

/OK3568_Linux_fs/kernel/drivers/mtd/maps/
H A Dphysmap-bt1-rom.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Baikal-T1 Physically Mapped Internal ROM driver
22 #include "physmap-bt1-rom.h"
25 * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions.
26 * We have to take this into account when implementing the data read-methods.
27 * Note there is no need in bothering with endianness, since both Baikal-T1
33 void __iomem *src = map->virt + ofs; in bt1_rom_map_read()
34 unsigned long shift; in bt1_rom_map_read() local
36 u32 data; in bt1_rom_map_read() local
38 /* Read data within offset dword. */ in bt1_rom_map_read()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Daxg.c1 // SPDX-License-Identifier: GPL-2.0+
3 * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
27 .data = &(struct meson_clk_pll_data){
30 .shift = 30,
35 .shift = 0,
[all …]
H A Dgxbb.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
87 .data = &(struct meson_clk_pll_data){
90 .shift = 30,
95 .shift = 0,
[all …]
H A Dg12a.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-G12A Clock Controller Driver
13 #include <linux/clk-provider.h>
20 #include "clk-mpll.h"
21 #include "clk-pll.h"
22 #include "clk-regmap.h"
23 #include "clk-cpu-dyndiv.h"
24 #include "vid-pll-div.h"
25 #include "meson-eeclk.h"
31 .data = &(struct meson_clk_pll_data){
[all …]
H A Dg12a-aoclk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
17 #include "g12a-aoclk.h"
19 #include "clk-regmap.h"
20 #include "clk-dualdiv.h"
24 * Register offsets from the data sheet must be multiplied by 4.
46 .data = &(struct clk_regmap_gate_data) { \
[all …]
H A Dmeson8b.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <linux/reset-controller.h>
20 #include "clk-regmap.h"
21 #include "clk-pll.h"
22 #include "clk-mpll.h"
65 .data = &(struct meson_clk_pll_data){
68 .shift = 30,
73 .shift = 0,
78 .shift = 9,
[all …]
H A Daxg-aoclk.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Amlogic Meson-AXG Clock Controller Driver
11 #include <linux/clk-provider.h>
13 #include <linux/reset-controller.h>
16 #include "meson-aoclk.h"
17 #include "axg-aoclk.h"
19 #include "clk-regmap.h"
20 #include "clk-dualdiv.h"
24 * Register offsets from the data sheet must be multiplied by 4.
37 .data = &(struct clk_regmap_gate_data) { \
[all …]
H A Dclk-regmap.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 #include <linux/clk-provider.h>
14 * struct clk_regmap - regmap backed clock
16 * @hw: handle between common and hardware-specific interfaces
18 * @data: data specific to the clock type
21 * of the clock is controlled by the clock_ops and data.
26 void *data; member
35 * struct clk_regmap_gate_data - regmap backed gate specific data
39 * @flags: hardware-specific flags
53 return (struct clk_regmap_gate_data *)clk->data; in clk_get_regmap_gate_data()
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/lib/
H A Dcsum.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 Arm Ltd.
5 #include <linux/kasan-checks.h>
10 /* Looks dumb, but generates nice-ish code */
11 static u64 accumulate(u64 sum, u64 data) in accumulate() argument
13 __uint128_t tmp = (__uint128_t)sum + data; in accumulate()
18 * We over-read the buffer and this makes KASAN unhappy. Instead, disable
23 unsigned int offset, shift, sum; in do_csum() local
25 u64 data, sum64 = 0; in do_csum() local
34 * should absolutely not be pointing to anything read-sensitive. We do, in do_csum()
[all …]
/OK3568_Linux_fs/kernel/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
24 #include "pinctrl-samsung.h"
112 .eint_mask = (1 << (pins)) - 1, \
136 .eint_mask = (1 << (pins)) - 1, \
190 .eint_mask = (1 << (pins)) - 1, \
196 * struct s3c64xx_eint0_data - EINT0 common data
197 * @drvdata: pin controller driver data
208 * struct s3c64xx_eint0_domain_data - EINT0 per-domain data
[all …]
/OK3568_Linux_fs/kernel/sound/soc/sprd/
H A Dsprd-mcdt.c1 // SPDX-License-Identifier: GPL-2.0
14 #include "sprd-mcdt.h"
121 u32 orig = readl_relaxed(mcdt->base + reg); in sprd_mcdt_update()
125 writel_relaxed(tmp, mcdt->base + reg); in sprd_mcdt_update()
155 u32 shift = MCDT_DAC_DMA_SHIFT + channel; in sprd_mcdt_dac_dma_enable() local
158 sprd_mcdt_update(mcdt, MCDT_DMA_EN, BIT(shift), BIT(shift)); in sprd_mcdt_dac_dma_enable()
160 sprd_mcdt_update(mcdt, MCDT_DMA_EN, 0, BIT(shift)); in sprd_mcdt_dac_dma_enable()
187 writel_relaxed(val, mcdt->base + reg); in sprd_mcdt_dac_write_fifo()
195 *val = readl_relaxed(mcdt->base + reg); in sprd_mcdt_adc_read_fifo()
298 u32 reg, shift = sprd_mcdt_dma_ack_shift(channel), ack = dma_chan; in sprd_mcdt_dac_dma_ack_select() local
[all …]
/OK3568_Linux_fs/kernel/arch/mips/pci/
H A Dops-vr41xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
5 * Copyright (C) 2001-2003 MontaVista Software Inc.
7 * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
12 * - New creation, NEC VR4122 and VR4131 are supported.
30 return -EINVAL; in set_pci_configuration_address()
39 return -EINVAL; in set_pci_configuration_address()
51 uint32_t data; in pci_config_read() local
54 if (set_pci_configuration_address(bus->number, devfn, where) < 0) in pci_config_read()
57 data = readl(PCICONFDREG); in pci_config_read()
[all …]
/OK3568_Linux_fs/kernel/arch/sh/drivers/pci/
H A Dops-sh4.c1 // SPDX-License-Identifier: GPL-2.0
3 * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780).
5 * Copyright (C) 2002 - 2009 Paul Mundt
11 #include "pci-sh4.h"
17 (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
25 struct pci_channel *chan = bus->sysdata; in sh4_pci_read()
27 u32 data; in sh4_pci_read() local
35 data = pci_read_reg(chan, SH4_PCIPDR); in sh4_pci_read()
40 *val = (data >> ((where & 3) << 3)) & 0xff; in sh4_pci_read()
43 *val = (data >> ((where & 2) << 3)) & 0xffff; in sh4_pci_read()
[all …]
/OK3568_Linux_fs/kernel/drivers/hwmon/
H A Dasc7621.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * asc7621.c - Part of lm_sensors, Linux kernel modules for hardware monitoring
13 #include <linux/hwmon-sysfs.h>
71 * and data arrays.
72 * This comes from the data sheet register description table.
110 u8 shift[3]; member
125 dev_err(&client->dev, in read_byte()
132 static inline int write_byte(struct i2c_client *client, u8 reg, u8 data) in write_byte() argument
134 int res = i2c_smbus_write_byte_data(client, reg, data); in write_byte()
136 dev_err(&client->dev, in write_byte()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dnv50.c29 struct nvkm_device *device = gpio->subdev.device; in nv50_gpio_reset()
30 struct nvkm_bios *bios = device->bios; in nv50_gpio_reset()
33 int ent = -1; in nv50_gpio_reset()
37 u32 data = nvbios_rd32(bios, entry); in nv50_gpio_reset() local
38 u8 line = (data & 0x0000001f); in nv50_gpio_reset()
39 u8 func = (data & 0x0000ff00) >> 8; in nv50_gpio_reset()
40 u8 defs = !!(data & 0x01000000); in nv50_gpio_reset()
41 u8 unk0 = !!(data & 0x02000000); in nv50_gpio_reset()
42 u8 unk1 = !!(data & 0x04000000); in nv50_gpio_reset()
58 nv50_gpio_location(int line, u32 *reg, u32 *shift) in nv50_gpio_location() argument
[all …]
/OK3568_Linux_fs/kernel/kernel/time/
H A Dvsyscall.c1 // SPDX-License-Identifier: GPL-2.0
24 vdata[CS_HRES_COARSE].cycle_last = tk->tkr_mono.cycle_last; in update_vdso_data()
25 vdata[CS_HRES_COARSE].mask = tk->tkr_mono.mask; in update_vdso_data()
26 vdata[CS_HRES_COARSE].mult = tk->tkr_mono.mult; in update_vdso_data()
27 vdata[CS_HRES_COARSE].shift = tk->tkr_mono.shift; in update_vdso_data()
28 vdata[CS_RAW].cycle_last = tk->tkr_raw.cycle_last; in update_vdso_data()
29 vdata[CS_RAW].mask = tk->tkr_raw.mask; in update_vdso_data()
30 vdata[CS_RAW].mult = tk->tkr_raw.mult; in update_vdso_data()
31 vdata[CS_RAW].shift = tk->tkr_raw.shift; in update_vdso_data()
35 vdso_ts->sec = tk->xtime_sec + tk->wall_to_monotonic.tv_sec; in update_vdso_data()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mmc/
H A Dexynos-dw-mshc.txt7 by synopsys-dw-mshc.txt and the properties used by the Samsung Exynos specific
13 - "samsung,exynos4210-dw-mshc": for controllers with Samsung Exynos4210
15 - "samsung,exynos4412-dw-mshc": for controllers with Samsung Exynos4412
17 - "samsung,exynos5250-dw-mshc": for controllers with Samsung Exynos5250
19 - "samsung,exynos5420-dw-mshc": for controllers with Samsung Exynos5420
21 - "samsung,exynos7-dw-mshc": for controllers with Samsung Exynos7
23 - "samsung,exynos7-dw-mshc-smu": for controllers with Samsung Exynos7
26 * samsung,dw-mshc-ciu-div: Specifies the divider value for the card interface
30 * samsung,dw-mshc-sdr-timing: Specifies the value of CIU clock phase shift value
31 in transmit mode and CIU clock phase shift value in receive mode for single
[all …]
/OK3568_Linux_fs/kernel/sound/soc/
H A Dsoc-ops.c1 // SPDX-License-Identifier: GPL-2.0+
3 // soc-ops.c -- Generic ASoC operations
11 // with code, comments and ideas from :-
27 #include <sound/soc-dpcm.h>
31 * snd_soc_info_enum_double - enumerated double mixer info callback
43 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in snd_soc_info_enum_double()
45 return snd_ctl_enum_info(uinfo, e->shift_l == e->shift_r ? 1 : 2, in snd_soc_info_enum_double()
46 e->items, e->texts); in snd_soc_info_enum_double()
51 * snd_soc_get_enum_double - enumerated double mixer get callback
63 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in snd_soc_get_enum_double()
[all …]
/OK3568_Linux_fs/kernel/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_ci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * DVB CAM support for NetUP Universal Dual DVB-CI
43 /* BIT_CAM_BYPASS bit shift for SLOT 1 */
48 writew(0x101, ndev->bmmio0 + CAM_CTRLSTAT_CLR); in netup_ci_interrupt()
55 struct netup_ci_state *state = en50221->data; in netup_unidvb_ci_slot_ts_ctl()
56 struct netup_unidvb_dev *dev = state->dev; in netup_unidvb_ci_slot_ts_ctl()
57 u16 shift = (state->nr == 1) ? CAM1_SHIFT : 0; in netup_unidvb_ci_slot_ts_ctl() local
59 dev_dbg(&dev->pci_dev->dev, "%s(): CAM_CTRLSTAT=0x%x\n", in netup_unidvb_ci_slot_ts_ctl()
60 __func__, readw(dev->bmmio0 + CAM_CTRLSTAT_READ_SET)); in netup_unidvb_ci_slot_ts_ctl()
62 return -EINVAL; in netup_unidvb_ci_slot_ts_ctl()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1)
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
26 * @shift: shift to the divider bit field
35 u8 shift; member
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
54 return divider_recalc_rate(hw, parent_rate, val, dclk->table, in hi6220_clkdiv_recalc_rate()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/os_dep/linux/
H A Dioctl_efuse.c3 * Copyright(c) 2007 - 2020 Realtek Corporation.
24 pefuse_arg->mp_class = RTW_MP_CLASS_EFUSE; in rtw_efuse_cmd()
25 pefuse_arg->cmd = cmdid; in rtw_efuse_cmd()
26 pefuse_arg->cmd_ok = 0; in rtw_efuse_cmd()
34 if (pefuse_arg->cmd_ok && pefuse_arg->status == RTW_PHL_STATUS_SUCCESS) { in rtw_efuse_cmd()
60 if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { in rtw_efuse_get_map_size()
61 *size = efuse_arg->io_value; in rtw_efuse_get_map_size()
89 if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { in rtw_efuse_get_available_size()
90 *size = efuse_arg->io_value; in rtw_efuse_get_available_size()
117 if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) in rtw_efuse_fake2map()
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/os_dep/linux/
H A Dioctl_efuse.c3 * Copyright(c) 2007 - 2020 Realtek Corporation.
24 pefuse_arg->mp_class = RTW_MP_CLASS_EFUSE; in rtw_efuse_cmd()
25 pefuse_arg->cmd = cmdid; in rtw_efuse_cmd()
26 pefuse_arg->cmd_ok = 0; in rtw_efuse_cmd()
34 if (pefuse_arg->cmd_ok && pefuse_arg->status == RTW_PHL_STATUS_SUCCESS) { in rtw_efuse_cmd()
60 if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { in rtw_efuse_get_map_size()
61 *size = efuse_arg->io_value; in rtw_efuse_get_map_size()
89 if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) { in rtw_efuse_get_available_size()
90 *size = efuse_arg->io_value; in rtw_efuse_get_available_size()
117 if (efuse_arg->cmd_ok && efuse_arg->status == RTW_PHL_STATUS_SUCCESS) in rtw_efuse_fake2map()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Dvc.h1 /* SPDX-License-Identifier: GPL-2.0-only */
22 * struct omap_vc_common - per-VC register/bitfield data
26 * @data_shift: DATA field shift in PRM_VC_BYPASS_VAL register
27 * @slaveaddr_shift: SLAVEADDR field shift in PRM_VC_BYPASS_VAL register
28 * @regaddr_shift: REGADDR field shift in PRM_VC_BYPASS_VAL register
29 * @cmd_on_shift: ON field shift in PRM_VC_CMD_VAL_* register
30 * @cmd_onlp_shift: ONLP field shift in PRM_VC_CMD_VAL_* register
31 * @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
32 * @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
34 * @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
43 * struct clk_rate_request - Structure encoding the clk constraints that
65 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
76 * struct clk_ops - Callback operations for hardware clocks; these are to
[all …]
/OK3568_Linux_fs/kernel/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-jtag.c8 * Copyright (c) 2003-2008 Cavium Networks
15 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
22 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-helper-jtag.h>
50 uint32_t divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000); in cvmx_helper_qlm_jtag_init()
51 divisor = (divisor - 1) >> 2; in cvmx_helper_qlm_jtag_init()
52 /* Convert the divisor into a power of 2 shift */ in cvmx_helper_qlm_jtag_init()
75 * into the MSB and out the LSB, so you should shift in the low
79 * @qlm: QLM to shift value into
80 * @bits: Number of bits to shift in (1-32).
[all …]

12345678910>>...43