clk/meson/axg.c

1 // SPDX-License-Identifier: GPL-2.0+
3  * AmLogic Meson-AXG Clock Controller Driver
12 #include <linux/clk-provider.h>
18 #include "clk-regmap.h"
19 #include "clk-pll.h"
20 #include "clk-mpll.h"
22 #include "meson-eeclk.h"
27 	.data = &(struct meson_clk_pll_data){
30 			.shift   = 30,
35 			.shift   = 0,
40 			.shift   = 9,
45 			.shift   = 0,
50 			.shift   = 31,
55 			.shift   = 29,
70 	.data = &(struct clk_regmap_div_data){
72 		.shift = 16,
91 	.data = &(struct meson_clk_pll_data){
94 			.shift   = 30,
99 			.shift   = 0,
104 			.shift   = 9,
109 			.shift   = 31,
114 			.shift   = 29,
129 	.data = &(struct clk_regmap_div_data){
131 		.shift = 16,
188 	.data = &(struct meson_clk_pll_data){
191 			.shift   = 30,
196 			.shift   = 0,
201 			.shift   = 9,
206 			.shift   = 0,
211 			.shift   = 31,
216 			.shift   = 29,
234 	.data = &(struct clk_regmap_div_data){
236 		.shift = 16,
260 	.data = &(struct meson_clk_pll_data){
263 			.shift   = 30,
268 			.shift   = 0,
273 			.shift   = 9,
278 			.shift   = 0,
283 			.shift   = 31,
288 			.shift   = 29,
307 	.data = &(struct clk_regmap_div_data){
309 		.shift = 16,
336 	.data = &(struct clk_regmap_gate_data){
363 	.data = &(struct clk_regmap_gate_data){
382 		 * b) CCF has a clock hand-off mechanism to make the sure the
401 	.data = &(struct clk_regmap_gate_data){
427 	.data = &(struct clk_regmap_gate_data){
455 	.data = &(struct clk_regmap_gate_data){
470 	.data = &(struct clk_regmap_div_data){
472 		.shift = 12,
486 	.data = &(struct meson_clk_mpll_data){
489 			.shift   = 0,
494 			.shift   = 15,
499 			.shift   = 16,
504 			.shift   = 0,
521 	.data = &(struct clk_regmap_gate_data){
537 	.data = &(struct meson_clk_mpll_data){
540 			.shift   = 0,
545 			.shift   = 15,
550 			.shift   = 16,
555 			.shift   = 1,
572 	.data = &(struct clk_regmap_gate_data){
588 	.data = &(struct meson_clk_mpll_data){
591 			.shift   = 0,
596 			.shift   = 15,
601 			.shift   = 16,
606 			.shift   = 25,
611 			.shift   = 2,
628 	.data = &(struct clk_regmap_gate_data){
644 	.data = &(struct meson_clk_mpll_data){
647 			.shift   = 12,
652 			.shift   = 11,
657 			.shift   = 2,
662 			.shift   = 3,
679 	.data = &(struct clk_regmap_gate_data){
713 	.data = &(struct meson_clk_pll_data){
716 			.shift   = 30,
721 			.shift   = 0,
726 			.shift   = 9,
731 			.shift   = 0,
736 			.shift   = 31,
741 			.shift   = 29,
759 	.data = &(struct clk_regmap_div_data){
761 		.shift = 16,
777 	.data = &(struct clk_regmap_div_data){
779 		.shift = 6,
795 	.data = &(struct clk_regmap_mux_data){
798 		.shift = 2,
812 	.data = &(struct clk_regmap_mux_data){
815 		.shift = 1,
829 	.data = &(struct clk_regmap_gate_data){
844 	.data = &(struct clk_regmap_gate_data){
869 	.data = &(struct clk_regmap_mux_data){
872 		.shift = 12,
884 	.data = &(struct clk_regmap_div_data){
886 		.shift = 0,
901 	.data = &(struct clk_regmap_gate_data){
932 	.data = &(struct clk_regmap_mux_data){
935 		.shift = 25,
947 	.data = &(struct clk_regmap_div_data){
949 		.shift = 16,
965 	.data = &(struct clk_regmap_gate_data){
982 	.data = &(struct clk_regmap_mux_data){
985 		.shift = 9,
997 	.data = &(struct clk_regmap_div_data){
999 		.shift = 0,
1015 	.data = &(struct clk_regmap_gate_data){
1047 	.data = &(struct clk_regmap_mux_data){
1050 		.shift = 12,
1068 	.data = &(struct clk_regmap_div_data){
1070 		.shift = 0,
1085 	.data = &(struct clk_regmap_gate_data){
1355 	{ .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
1363 		.name	= "axg-clkc",