1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2001-2003 MontaVista Software Inc.
6*4882a593Smuzhiyun * Author: Yoichi Yuasa <source@mvista.com>
7*4882a593Smuzhiyun * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@linux-mips.org>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun /*
10*4882a593Smuzhiyun * Changes:
11*4882a593Smuzhiyun * MontaVista Software Inc. <source@mvista.com>
12*4882a593Smuzhiyun * - New creation, NEC VR4122 and VR4131 are supported.
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun #include <linux/pci.h>
15*4882a593Smuzhiyun #include <linux/types.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <asm/io.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14)
20*4882a593Smuzhiyun #define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
21*4882a593Smuzhiyun
set_pci_configuration_address(unsigned char number,unsigned int devfn,int where)22*4882a593Smuzhiyun static inline int set_pci_configuration_address(unsigned char number,
23*4882a593Smuzhiyun unsigned int devfn, int where)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun if (number == 0) {
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * Type 0 configuration
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun if (PCI_SLOT(devfn) < 11 || where > 0xff)
30*4882a593Smuzhiyun return -EINVAL;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun writel((1U << PCI_SLOT(devfn)) | (PCI_FUNC(devfn) << 8) |
33*4882a593Smuzhiyun (where & 0xfc), PCICONFAREG);
34*4882a593Smuzhiyun } else {
35*4882a593Smuzhiyun /*
36*4882a593Smuzhiyun * Type 1 configuration
37*4882a593Smuzhiyun */
38*4882a593Smuzhiyun if (where > 0xff)
39*4882a593Smuzhiyun return -EINVAL;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun writel(((uint32_t)number << 16) | ((devfn & 0xff) << 8) |
42*4882a593Smuzhiyun (where & 0xfc) | 1U, PCICONFAREG);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun return 0;
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
pci_config_read(struct pci_bus * bus,unsigned int devfn,int where,int size,uint32_t * val)48*4882a593Smuzhiyun static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
49*4882a593Smuzhiyun int size, uint32_t *val)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun uint32_t data;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun *val = 0xffffffffU;
54*4882a593Smuzhiyun if (set_pci_configuration_address(bus->number, devfn, where) < 0)
55*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun data = readl(PCICONFDREG);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun switch (size) {
60*4882a593Smuzhiyun case 1:
61*4882a593Smuzhiyun *val = (data >> ((where & 3) << 3)) & 0xffU;
62*4882a593Smuzhiyun break;
63*4882a593Smuzhiyun case 2:
64*4882a593Smuzhiyun *val = (data >> ((where & 2) << 3)) & 0xffffU;
65*4882a593Smuzhiyun break;
66*4882a593Smuzhiyun case 4:
67*4882a593Smuzhiyun *val = data;
68*4882a593Smuzhiyun break;
69*4882a593Smuzhiyun default:
70*4882a593Smuzhiyun return PCIBIOS_FUNC_NOT_SUPPORTED;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
pci_config_write(struct pci_bus * bus,unsigned int devfn,int where,int size,uint32_t val)76*4882a593Smuzhiyun static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
77*4882a593Smuzhiyun int size, uint32_t val)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun uint32_t data;
80*4882a593Smuzhiyun int shift;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (set_pci_configuration_address(bus->number, devfn, where) < 0)
83*4882a593Smuzhiyun return PCIBIOS_DEVICE_NOT_FOUND;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun data = readl(PCICONFDREG);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun switch (size) {
88*4882a593Smuzhiyun case 1:
89*4882a593Smuzhiyun shift = (where & 3) << 3;
90*4882a593Smuzhiyun data &= ~(0xffU << shift);
91*4882a593Smuzhiyun data |= ((val & 0xffU) << shift);
92*4882a593Smuzhiyun break;
93*4882a593Smuzhiyun case 2:
94*4882a593Smuzhiyun shift = (where & 2) << 3;
95*4882a593Smuzhiyun data &= ~(0xffffU << shift);
96*4882a593Smuzhiyun data |= ((val & 0xffffU) << shift);
97*4882a593Smuzhiyun break;
98*4882a593Smuzhiyun case 4:
99*4882a593Smuzhiyun data = val;
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun default:
102*4882a593Smuzhiyun return PCIBIOS_FUNC_NOT_SUPPORTED;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun writel(data, PCICONFDREG);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return PCIBIOS_SUCCESSFUL;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct pci_ops vr41xx_pci_ops = {
111*4882a593Smuzhiyun .read = pci_config_read,
112*4882a593Smuzhiyun .write = pci_config_write,
113*4882a593Smuzhiyun };
114