1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2018 BayLibre, SAS.
4*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com>
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #ifndef __CLK_REGMAP_H
8*4882a593Smuzhiyun #define __CLK_REGMAP_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/clk-provider.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /**
14*4882a593Smuzhiyun * struct clk_regmap - regmap backed clock
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * @hw: handle between common and hardware-specific interfaces
17*4882a593Smuzhiyun * @map: pointer to the regmap structure controlling the clock
18*4882a593Smuzhiyun * @data: data specific to the clock type
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Clock which is controlled by regmap backed registers. The actual type of
21*4882a593Smuzhiyun * of the clock is controlled by the clock_ops and data.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun struct clk_regmap {
24*4882a593Smuzhiyun struct clk_hw hw;
25*4882a593Smuzhiyun struct regmap *map;
26*4882a593Smuzhiyun void *data;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
to_clk_regmap(struct clk_hw * hw)29*4882a593Smuzhiyun static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun return container_of(hw, struct clk_regmap, hw);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /**
35*4882a593Smuzhiyun * struct clk_regmap_gate_data - regmap backed gate specific data
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * @offset: offset of the register controlling gate
38*4882a593Smuzhiyun * @bit_idx: single bit controlling gate
39*4882a593Smuzhiyun * @flags: hardware-specific flags
40*4882a593Smuzhiyun *
41*4882a593Smuzhiyun * Flags:
42*4882a593Smuzhiyun * Same as clk_gate except CLK_GATE_HIWORD_MASK which is ignored
43*4882a593Smuzhiyun */
44*4882a593Smuzhiyun struct clk_regmap_gate_data {
45*4882a593Smuzhiyun unsigned int offset;
46*4882a593Smuzhiyun u8 bit_idx;
47*4882a593Smuzhiyun u8 flags;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static inline struct clk_regmap_gate_data *
clk_get_regmap_gate_data(struct clk_regmap * clk)51*4882a593Smuzhiyun clk_get_regmap_gate_data(struct clk_regmap *clk)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun return (struct clk_regmap_gate_data *)clk->data;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun extern const struct clk_ops clk_regmap_gate_ops;
57*4882a593Smuzhiyun extern const struct clk_ops clk_regmap_gate_ro_ops;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /**
60*4882a593Smuzhiyun * struct clk_regmap_div_data - regmap backed adjustable divider specific data
61*4882a593Smuzhiyun *
62*4882a593Smuzhiyun * @offset: offset of the register controlling the divider
63*4882a593Smuzhiyun * @shift: shift to the divider bit field
64*4882a593Smuzhiyun * @width: width of the divider bit field
65*4882a593Smuzhiyun * @table: array of value/divider pairs, last entry should have div = 0
66*4882a593Smuzhiyun *
67*4882a593Smuzhiyun * Flags:
68*4882a593Smuzhiyun * Same as clk_divider except CLK_DIVIDER_HIWORD_MASK which is ignored
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun struct clk_regmap_div_data {
71*4882a593Smuzhiyun unsigned int offset;
72*4882a593Smuzhiyun u8 shift;
73*4882a593Smuzhiyun u8 width;
74*4882a593Smuzhiyun u8 flags;
75*4882a593Smuzhiyun const struct clk_div_table *table;
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static inline struct clk_regmap_div_data *
clk_get_regmap_div_data(struct clk_regmap * clk)79*4882a593Smuzhiyun clk_get_regmap_div_data(struct clk_regmap *clk)
80*4882a593Smuzhiyun {
81*4882a593Smuzhiyun return (struct clk_regmap_div_data *)clk->data;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun extern const struct clk_ops clk_regmap_divider_ops;
85*4882a593Smuzhiyun extern const struct clk_ops clk_regmap_divider_ro_ops;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /**
88*4882a593Smuzhiyun * struct clk_regmap_mux_data - regmap backed multiplexer clock specific data
89*4882a593Smuzhiyun *
90*4882a593Smuzhiyun * @hw: handle between common and hardware-specific interfaces
91*4882a593Smuzhiyun * @offset: offset of theregister controlling multiplexer
92*4882a593Smuzhiyun * @table: array of parent indexed register values
93*4882a593Smuzhiyun * @shift: shift to multiplexer bit field
94*4882a593Smuzhiyun * @mask: mask of mutliplexer bit field
95*4882a593Smuzhiyun * @flags: hardware-specific flags
96*4882a593Smuzhiyun *
97*4882a593Smuzhiyun * Flags:
98*4882a593Smuzhiyun * Same as clk_divider except CLK_MUX_HIWORD_MASK which is ignored
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun struct clk_regmap_mux_data {
101*4882a593Smuzhiyun unsigned int offset;
102*4882a593Smuzhiyun u32 *table;
103*4882a593Smuzhiyun u32 mask;
104*4882a593Smuzhiyun u8 shift;
105*4882a593Smuzhiyun u8 flags;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static inline struct clk_regmap_mux_data *
clk_get_regmap_mux_data(struct clk_regmap * clk)109*4882a593Smuzhiyun clk_get_regmap_mux_data(struct clk_regmap *clk)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun return (struct clk_regmap_mux_data *)clk->data;
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun extern const struct clk_ops clk_regmap_mux_ops;
115*4882a593Smuzhiyun extern const struct clk_ops clk_regmap_mux_ro_ops;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \
118*4882a593Smuzhiyun struct clk_regmap _name = { \
119*4882a593Smuzhiyun .data = &(struct clk_regmap_gate_data){ \
120*4882a593Smuzhiyun .offset = (_reg), \
121*4882a593Smuzhiyun .bit_idx = (_bit), \
122*4882a593Smuzhiyun }, \
123*4882a593Smuzhiyun .hw.init = &(struct clk_init_data) { \
124*4882a593Smuzhiyun .name = #_name, \
125*4882a593Smuzhiyun .ops = _ops, \
126*4882a593Smuzhiyun .parent_hws = (const struct clk_hw *[]) { _pname }, \
127*4882a593Smuzhiyun .num_parents = 1, \
128*4882a593Smuzhiyun .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
129*4882a593Smuzhiyun }, \
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun #define MESON_PCLK(_name, _reg, _bit, _pname) \
133*4882a593Smuzhiyun __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \
136*4882a593Smuzhiyun __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
137*4882a593Smuzhiyun #endif /* __CLK_REGMAP_H */
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