Lines Matching +full:data +full:- +full:shift
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
87 .data = &(struct meson_clk_pll_data){
90 .shift = 30,
95 .shift = 0,
100 .shift = 9,
105 .shift = 0,
110 .shift = 31,
115 .shift = 29,
130 .data = &(struct clk_regmap_div_data){
132 .shift = 16,
164 .data = &(struct meson_clk_pll_data){
167 .shift = 30,
172 .shift = 0,
177 .shift = 9,
182 .shift = 0,
187 .shift = 31,
192 .shift = 28,
212 .data = &(struct meson_clk_pll_data){
215 .shift = 30,
220 .shift = 0,
225 .shift = 9,
229 * On gxl, there is a register shift due to
236 .shift = 0,
241 .shift = 31,
246 .shift = 28,
266 .data = &(struct clk_regmap_div_data){
268 .shift = 16,
284 .data = &(struct clk_regmap_div_data){
286 .shift = 22,
302 .data = &(struct clk_regmap_div_data){
304 .shift = 18,
320 .data = &(struct clk_regmap_div_data){
322 .shift = 21,
338 .data = &(struct clk_regmap_div_data){
340 .shift = 23,
356 .data = &(struct clk_regmap_div_data){
358 .shift = 19,
374 .data = &(struct meson_clk_pll_data){
377 .shift = 30,
382 .shift = 0,
387 .shift = 9,
392 .shift = 31,
397 .shift = 29,
412 .data = &(struct clk_regmap_div_data){
414 .shift = 10,
436 .data = &(struct meson_clk_pll_data){
439 .shift = 30,
444 .shift = 0,
449 .shift = 9,
454 .shift = 31,
459 .shift = 29,
485 .data = &(struct meson_clk_pll_data){
488 .shift = 30,
493 .shift = 0,
498 .shift = 9,
503 .shift = 0,
508 .shift = 31,
513 .shift = 29,
531 .data = &(struct clk_regmap_div_data){
533 .shift = 16,
549 .index = -1,
570 .data = &(struct clk_regmap_gate_data){
597 .data = &(struct clk_regmap_gate_data){
616 * b) CCF has a clock hand-off mechanism to make the sure the
635 .data = &(struct clk_regmap_gate_data){
661 .data = &(struct clk_regmap_gate_data){
687 .data = &(struct clk_regmap_gate_data){
702 .data = &(struct clk_regmap_div_data){
704 .shift = 12,
716 .data = &(struct meson_clk_mpll_data){
719 .shift = 0,
724 .shift = 25,
729 .shift = 16,
745 .data = &(struct meson_clk_mpll_data){
748 .shift = 0,
753 .shift = 15,
758 .shift = 16,
774 .data = &(struct clk_regmap_gate_data){
789 .index = -1,
797 .data = &(struct meson_clk_mpll_data){
800 .shift = 0,
805 .shift = 15,
810 .shift = 16,
826 .data = &(struct clk_regmap_gate_data){
840 .data = &(struct meson_clk_mpll_data){
843 .shift = 0,
848 .shift = 15,
853 .shift = 16,
869 .data = &(struct clk_regmap_gate_data){
894 .data = &(struct clk_regmap_mux_data){
897 .shift = 12,
914 .data = &(struct clk_regmap_div_data){
916 .shift = 0,
931 .data = &(struct clk_regmap_gate_data){
947 .data = &(struct clk_regmap_mux_data){
950 .shift = 9,
965 .data = &(struct clk_regmap_div_data){
967 .shift = 0,
982 .data = &(struct clk_regmap_gate_data){
999 * muxed by a glitch-free switch. The CCF can manage this glitch-free
1000 * mux because it does top-to-bottom updates the each clock tree and
1016 .data = &(struct clk_regmap_mux_data){
1019 .shift = 9,
1037 .data = &(struct clk_regmap_div_data){
1039 .shift = 0,
1054 .data = &(struct clk_regmap_gate_data){
1070 .data = &(struct clk_regmap_mux_data){
1073 .shift = 25,
1091 .data = &(struct clk_regmap_div_data){
1093 .shift = 16,
1108 .data = &(struct clk_regmap_gate_data){
1129 .data = &(struct clk_regmap_mux_data){
1132 .shift = 31,
1144 .data = &(struct clk_regmap_mux_data){
1147 .shift = 9,
1164 .data = &(struct clk_regmap_div_data) {
1166 .shift = 0,
1182 .data = &(struct clk_regmap_gate_data){
1198 .data = &(struct clk_regmap_mux_data){
1201 .shift = 25,
1218 .data = &(struct clk_regmap_div_data){
1220 .shift = 16,
1236 .data = &(struct clk_regmap_gate_data){
1252 .data = &(struct clk_regmap_mux_data){
1255 .shift = 27,
1266 *The parent is specific to origin of the audio data. Let the
1280 { .name = "cts_slow_oscin", .index = -1 },
1286 .data = &(struct clk_regmap_mux_data){
1289 .shift = 16,
1301 .data = &(struct clk_regmap_div_data){
1303 .shift = 0,
1318 .data = &(struct clk_regmap_gate_data){
1349 .data = &(struct clk_regmap_mux_data){
1352 .shift = 9,
1364 .data = &(struct clk_regmap_div_data){
1366 .shift = 0,
1382 .data = &(struct clk_regmap_gate_data){
1399 .data = &(struct clk_regmap_mux_data){
1402 .shift = 25,
1414 .data = &(struct clk_regmap_div_data){
1416 .shift = 16,
1432 .data = &(struct clk_regmap_gate_data){
1449 .data = &(struct clk_regmap_mux_data){
1452 .shift = 9,
1464 .data = &(struct clk_regmap_div_data){
1466 .shift = 0,
1482 .data = &(struct clk_regmap_gate_data){
1507 .data = &(struct clk_regmap_mux_data){
1510 .shift = 9,
1526 .data = &(struct clk_regmap_div_data){
1528 .shift = 0,
1541 .data = &(struct clk_regmap_gate_data){
1555 .data = &(struct clk_regmap_mux_data){
1558 .shift = 25,
1574 .data = &(struct clk_regmap_div_data){
1576 .shift = 16,
1589 .data = &(struct clk_regmap_gate_data){
1603 .data = &(struct clk_regmap_mux_data){
1606 .shift = 31,
1634 .data = &(struct clk_regmap_mux_data){
1637 .shift = 9,
1653 .data = &(struct clk_regmap_div_data){
1655 .shift = 0,
1670 .data = &(struct clk_regmap_gate_data){
1686 .data = &(struct clk_regmap_mux_data){
1689 .shift = 25,
1705 .data = &(struct clk_regmap_div_data){
1707 .shift = 16,
1722 .data = &(struct clk_regmap_gate_data){
1738 .data = &(struct clk_regmap_mux_data){
1741 .shift = 31,
1760 .data = &(struct clk_regmap_gate_data){
1776 .data = &(struct meson_vid_pll_div_data){
1779 .shift = 0,
1784 .shift = 16,
1800 .index = -1,
1816 { .name = "hdmi_pll", .index = -1 },
1820 .data = &(struct clk_regmap_mux_data){
1823 .shift = 18,
1839 .data = &(struct clk_regmap_gate_data){
1865 .data = &(struct clk_regmap_mux_data){
1868 .shift = 16,
1885 .data = &(struct clk_regmap_mux_data){
1888 .shift = 16,
1905 .data = &(struct clk_regmap_gate_data){
1919 .data = &(struct clk_regmap_gate_data){
1933 .data = &(struct clk_regmap_div_data){
1935 .shift = 0,
1950 .data = &(struct clk_regmap_div_data){
1952 .shift = 0,
1967 .data = &(struct clk_regmap_gate_data){
1981 .data = &(struct clk_regmap_gate_data){
1995 .data = &(struct clk_regmap_gate_data){
2009 .data = &(struct clk_regmap_gate_data){
2023 .data = &(struct clk_regmap_gate_data){
2037 .data = &(struct clk_regmap_gate_data){
2051 .data = &(struct clk_regmap_gate_data){
2065 .data = &(struct clk_regmap_gate_data){
2079 .data = &(struct clk_regmap_gate_data){
2093 .data = &(struct clk_regmap_gate_data){
2107 .data = &(struct clk_regmap_gate_data){
2121 .data = &(struct clk_regmap_gate_data){
2253 .data = &(struct clk_regmap_mux_data){
2256 .shift = 28,
2269 .data = &(struct clk_regmap_mux_data){
2272 .shift = 20,
2285 .data = &(struct clk_regmap_mux_data){
2288 .shift = 28,
2316 .data = &(struct clk_regmap_mux_data){
2319 .shift = 16,
2338 .data = &(struct clk_regmap_gate_data){
2354 .data = &(struct clk_regmap_gate_data){
2370 .data = &(struct clk_regmap_gate_data){
2386 .data = &(struct clk_regmap_gate_data){
2411 .data = &(struct clk_regmap_mux_data){
2414 .shift = 9,
2427 .data = &(struct clk_regmap_div_data){
2429 .shift = 0,
2442 .data = &(struct clk_regmap_gate_data){
2465 .data = &(struct clk_regmap_mux_data){
2468 .shift = 9,
2481 .data = &(struct clk_regmap_div_data){
2483 .shift = 0,
2499 .data = &(struct clk_regmap_gate_data){
2515 .data = &(struct clk_regmap_mux_data){
2518 .shift = 25,
2531 .data = &(struct clk_regmap_div_data){
2533 .shift = 16,
2549 .data = &(struct clk_regmap_gate_data){
2581 .data = &(struct clk_regmap_mux_data){
2584 .shift = 12,
2602 .data = &(struct clk_regmap_div_data){
2604 .shift = 0,
2619 .data = &(struct clk_regmap_gate_data){
3557 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3558 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3566 .name = "gxbb-clkc",