1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
43  * struct clk_rate_request - Structure encoding the clk constraints that
65  * struct clk_duty - Struture encoding the duty cycle ratio of a clock
76  * struct clk_ops -  Callback operations for hardware clocks; these are to
123  *		Returns the calculated rate.  Optional, but recommended - if
139  *		Returns 0 on success, -EERROR otherwise.
155  *		Returns 0 on success, -EERROR otherwise.
166  *		Returns 0 on success, -EERROR otherwise.
171  *		Returns the calculated accuracy.  Optional - if	this op is not
176  *		Returned values are 0-359 degrees on success, negative
179  * @set_phase:	Shift the phase this clock signal in degrees specified
181  *		0-359. Return 0 on success, otherwise -EERROR.
190  *              and >= numerator) Return 0 on success, otherwise -EERROR.
192  * @init:	Perform platform-specific initialization magic.
199  *		Returns 0 on success, -EERROR otherwise.
203  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
207  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
211  *		its clock tree. Returns 0 on success, -EERROR otherwise.
215  *		was changing states. Returns 0 on success, -EERROR otherwise.
272  * struct clk_parent_data - clk parent information
286  * struct clk_init_data - holds init data that's common to all clocks and is
292  * @parent_data: array of parent data for all possible parents (when some
297  * @flags: framework-level hints and quirks
311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
312  * hardware-specific structure.  struct clk_hw should be declared within struct
319  * @clk: pointer to the per-user struct clk instance that can be used to call
322  * @init: pointer to struct clk_init_data that contains the init data shared
342  * struct clk_fixed_rate - fixed-rate clock
343  * @hw:		handle between common and hardware-specific interfaces
349  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
372  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
377  * @flags: framework-specific flags
378  * @fixed_rate: non-adjustable clock rate
384  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
389  * @flags: framework-specific flags
390  * @fixed_rate: non-adjustable clock rate
397  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
401  * @parent_data: parent clk data
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
411  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
416  * @flags: framework-specific flags
417  * @fixed_rate: non-adjustable clock rate
418  * @fixed_accuracy: non-adjustable clock accuracy
427  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
432  * @flags: framework-specific flags
433  * @fixed_rate: non-adjustable clock rate
434  * @fixed_accuracy: non-adjustable clock accuracy
442  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
447  * @flags: framework-specific flags
448  * @fixed_rate: non-adjustable clock rate
449  * @fixed_accuracy: non-adjustable clock accuracy
463  * struct clk_gate - gating clock
465  * @hw:		handle between common and hardware-specific interfaces
468  * @flags:	hardware-specific flags
474  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
477  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
478  *	of this register, and mask of gate bits are in higher 16-bit of this
479  *	register.  While setting the gate bits, higher 16-bit should also be
481  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
512  * clk_hw_register_gate - register a gate clock with the clock framework
516  * @flags: framework-specific flags for this clock
519  * @clk_gate_flags: gate-specific flags for this clock
528  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
533  * @flags: framework-specific flags for this clock
536  * @clk_gate_flags: gate-specific flags for this clock
545  * clk_hw_register_gate_parent_data - register a gate clock with the clock
549  * @parent_data: parent clk data
550  * @flags: framework-specific flags for this clock
553  * @clk_gate_flags: gate-specific flags for this clock
571  * struct clk_divider - adjustable divider clock
573  * @hw:		handle between common and hardware-specific interfaces
575  * @shift:	shift to the divider bit field
584  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
588  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
590  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
595  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
596  *	of this register, and mask of divider bits are in higher 16-bit of this
597  *	register.  While setting the divider bits, higher 16-bit should also be
599  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
601  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
603  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
606  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
613 	u8		shift;  member
620 #define clk_div_mask(width)	((1 << (width)) - 1)
654 		void __iomem *reg, u8 shift, u8 width, u8 clk_divider_flags,
658 		void __iomem *reg, u8 shift, u8 width,
662  * clk_register_divider - register a divider clock with the clock framework
666  * @flags: framework-specific flags
668  * @shift: number of bits to shift the bitfield
670  * @clk_divider_flags: divider-specific flags for this clock
673 #define clk_register_divider(dev, name, parent_name, flags, reg, shift, width, \  argument
676 				   (reg), (shift), (width),		       \
679  * clk_hw_register_divider - register a divider clock with the clock framework
683  * @flags: framework-specific flags
685  * @shift: number of bits to shift the bitfield
687  * @clk_divider_flags: divider-specific flags for this clock
690 #define clk_hw_register_divider(dev, name, parent_name, flags, reg, shift,    \  argument
693 				  NULL, (flags), (reg), (shift), (width),     \
696  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
701  * @flags: framework-specific flags
703  * @shift: number of bits to shift the bitfield
705  * @clk_divider_flags: divider-specific flags for this clock
709 					  shift, width, clk_divider_flags,    \  argument
712 				  NULL, (flags), (reg), (shift), (width),     \
715  * clk_hw_register_divider_parent_data - register a divider clock with the clock
719  * @parent_data: parent clk data
720  * @flags: framework-specific flags
722  * @shift: number of bits to shift the bitfield
724  * @clk_divider_flags: divider-specific flags for this clock
728 					    reg, shift, width,		      \  argument
731 				  (parent_data), (flags), (reg), (shift),     \
734  * clk_hw_register_divider_table - register a table based divider clock with
739  * @flags: framework-specific flags
741  * @shift: number of bits to shift the bitfield
743  * @clk_divider_flags: divider-specific flags for this clock
748 				      shift, width, clk_divider_flags, table, \  argument
751 				  NULL, (flags), (reg), (shift), (width),     \
754  * clk_hw_register_divider_table_parent_hw - register a table based divider
759  * @flags: framework-specific flags
761  * @shift: number of bits to shift the bitfield
763  * @clk_divider_flags: divider-specific flags for this clock
768 						reg, shift, width,	      \  argument
772 				  NULL, (flags), (reg), (shift), (width),     \
775  * clk_hw_register_divider_table_parent_data - register a table based divider
779  * @parent_data: parent clk data
780  * @flags: framework-specific flags
782  * @shift: number of bits to shift the bitfield
784  * @clk_divider_flags: divider-specific flags for this clock
789 						  flags, reg, shift, width,   \  argument
793 				  (parent_data), (flags), (reg), (shift),     \
801  * struct clk_mux - multiplexer clock
803  * @hw:		handle between common and hardware-specific interfaces
806  * @shift:	shift to multiplexer bit field
808  * @flags:	hardware-specific flags
815  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
816  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
817  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
818  *	register, and mask of mux bits are in higher 16-bit of this register.
819  *	While setting the mux bits, higher 16-bit should also be updated to
821  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
823  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
825  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
834 	u8		shift;  member
856 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
860 		unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
864 			 shift, width, clk_mux_flags, lock)		      \  argument
866 			       (flags), (reg), (shift), BIT((width)) - 1,     \
869 				  flags, reg, shift, mask, clk_mux_flags,     \  argument
873 			      (shift), (mask), (clk_mux_flags), (table),      \
876 			    shift, width, clk_mux_flags, lock)		      \  argument
879 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
882 				reg, shift, width, clk_mux_flags, lock)	      \  argument
884 			      (parent_hws), NULL, (flags), (reg), (shift),    \
885 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
887 					flags, reg, shift, width,	      \  argument
890 			      (parent_data), (flags), (reg), (shift),	      \
891 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
903  * struct clk_fixed_factor - fixed multiplier and divider clock
905  * @hw:		handle between common and hardware-specific interfaces
933  * struct clk_fractional_divider - adjustable fractional divider clock
935  * @hw:		handle between common and hardware-specific interfaces
937  * @mshift:	shift to the numerator bit field
939  * @nshift:	shift to the denominator bit field
946  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
950  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
953  * CLK_FRAC_DIVIDER_NO_LIMIT - not need to follow the 20 times limit on
990  * struct clk_multiplier - adjustable multiplier clock
992  * @hw:		handle between common and hardware-specific interfaces
994  * @shift:	shift to the multiplier bit field
1002  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1007  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1009  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1016 	u8		shift;  member
1031  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1033  * @hw:		handle between common and hardware-specific interfaces
1034  * @mux_hw:	handle between composite and hardware-specific mux clock
1035  * @rate_hw:	handle between composite and hardware-specific rate clock
1036  * @gate_hw:	handle between composite and hardware-specific gate clock
1142 	dst->clk = src->clk;  in __clk_hw_set_clk()
1143 	dst->core = src->core;  in __clk_hw_set_clk()
1325 						   void *data),
1326 			void *data);
1329 						 void *data),
1330 			   void *data);
1333 						 void *data),
1334 			   void *data);
1338 				  void *data);
1340 				    void *data);
1341 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1343 				     void *data);
1353 						   void *data),  in of_clk_add_provider()  argument
1354 			void *data)  in of_clk_add_provider()
1360 					      void *data),  in of_clk_add_hw_provider()  argument
1361 			void *data)  in of_clk_add_hw_provider()
1367 						 void *data),  in devm_of_clk_add_hw_provider()  argument
1368 			   void *data)  in devm_of_clk_add_hw_provider()
1375 	struct of_phandle_args *clkspec, void *data)  in of_clk_src_simple_get()  argument
1377 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1380 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)  in of_clk_hw_simple_get()  argument
1382 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1385 	struct of_phandle_args *clkspec, void *data)  in of_clk_src_onecell_get()  argument
1387 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1390 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)  in of_clk_hw_onecell_get()  argument
1392 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()