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/OK3568_Linux_fs/kernel/sound/pci/lola/
H A Dlola_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Support for Digigram Lola PCI-e boards
17 unsigned int freq; in lola_sample_rate_convert() local
21 case 0: freq = 48000; break; in lola_sample_rate_convert()
22 case 1: freq = 44100; break; in lola_sample_rate_convert()
23 case 2: freq = 32000; break; in lola_sample_rate_convert()
31 case (1 << 2): freq *= 2; break; in lola_sample_rate_convert()
32 case (2 << 2): freq *= 4; break; in lola_sample_rate_convert()
33 case (5 << 2): freq /= 2; break; in lola_sample_rate_convert()
34 case (6 << 2): freq /= 4; break; in lola_sample_rate_convert()
[all …]
/OK3568_Linux_fs/kernel/sound/drivers/vx/
H A Dvx_uer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * vx_modify_board_clock - tell the board that its clock has been modified
32 * vx_modify_board_inputs - resync audio inputs
44 * vx_read_one_cbit - read one bit from UER config
52 mutex_lock(&chip->lock); in vx_read_one_cbit()
53 if (chip->type >= VX_TYPE_VXPOCKET) { in vx_read_one_cbit()
62 mutex_unlock(&chip->lock); in vx_read_one_cbit()
67 * vx_write_one_cbit - write one bit to UER config
74 mutex_lock(&chip->lock); in vx_write_one_cbit()
82 mutex_unlock(&chip->lock); in vx_write_one_cbit()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx5/
H A Dclock.c7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
70 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
78 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
81 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
92 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
108 return -EINVAL; in enable_i2c_clk()
112 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
114 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx7/
H A Dclock.c7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
31 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in get_clocks()
33 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in get_clocks()
35 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in get_clocks()
82 /* disable the clock gate first */ in enable_usboh3_clk()
92 /* enable the clock gate */ in enable_usboh3_clk()
116 reg = readl(&ccm_anatop->pll_arm); in decode_pll()
130 reg = readl(&ccm_anatop->pll_480); in decode_pll()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/mx6/
H A Dclock.c2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
37 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
45 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
55 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt3 - compatible: "rockchip,rk3288-dmc", "syscon"
4 - rockchip,cru: this driver should access cru regs, so need get cru here
5 - rockchip,grf: this driver should access grf regs, so need get grf here
6 - rockchip,pmu: this driver should access pmu regs, so need get pmu here
7 - rockchip,sgrf: this driver should access sgrf regs, so need get sgrf here
8 - rockchip,noc: this driver should access noc regs, so need get noc here
9 - reg: dynamic ram protocol controller(PCTL) address and phy controller(PHYCTL) address
10 - clock: must include clock specifiers corresponding to entries in the clock-names property.
11 - clock-output-names: from common clock binding to override the default output clock name
13 pclk_ddrupctl0: support clock for access protocol controller registers of channel 0
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-qcom-hw.txt8 - compatible
11 Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
13 - clocks
15 Value type: <phandle> From common clock binding.
16 Definition: clock handle for XO clock and GPLL0 clock.
18 - clock-names
20 Value type: <string> From common clock binding.
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
[all …]
/OK3568_Linux_fs/kernel/drivers/net/can/mscan/
H A Dmpc5xxx_can.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
7 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
36 { .compatible = "fsl,mpc5200-cdm", },
46 unsigned int freq; in mpc52xx_can_get_clock() local
52 * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock in mpc52xx_can_get_clock()
53 * (IP_CLK) can be selected as MSCAN clock source. According to in mpc52xx_can_get_clock()
54 * the MPC5200 user's manual, the oscillator clock is the better in mpc52xx_can_get_clock()
64 freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node); in mpc52xx_can_get_clock()
65 if (!freq) in mpc52xx_can_get_clock()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/
H A Dmsm_gpu_trace.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 __entry->pid = pid;
23 __entry->id = id;
24 __entry->ringid = ringid;
25 __entry->nr_bos = nr_bos;
26 __entry->nr_cmds = nr_cmds
29 __entry->id, __entry->pid, __entry->ringid,
30 __entry->nr_bos, __entry->nr_cmds)
44 __entry->pid = pid_nr(submit->pid);
45 __entry->id = submit->ident;
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/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c2 * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
21 u32 cpu = readl(&mscmir->cpxtype); in get_cpu_rev()
36 return -1; in get_pllfreq()
58 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq()
98 u32 freq = 0; in get_mcu_main_clk() local
110 freq = FIRC_CLK_FREQ; in get_mcu_main_clk()
113 freq = XOSC_CLK_FREQ; in get_mcu_main_clk()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7/vf610/
H A Dgeneric.c4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/clock.h>
12 #include <asm/mach-imx/sys_proto.h>
30 reg = readl(&ccm->ccgr6); in enable_ocotp_clk()
35 writel(reg, &ccm->ccgr6); in enable_ocotp_clk()
44 u32 freq = 0; in get_mcu_main_clk() local
46 ccm_ccsr = readl(&ccm->ccsr); in get_mcu_main_clk()
50 ccm_cacrr = readl(&ccm->cacrr); in get_mcu_main_clk()
57 freq = FASE_CLK_FREQ; in get_mcu_main_clk()
[all …]
/OK3568_Linux_fs/kernel/drivers/sh/clk/
H A Dcore.c2 * SuperH clock framework
4 * Copyright (C) 2005 - 2010 Paul Mundt
6 * This clock framework is derived from the OMAP version by:
8 * Copyright (C) 2004 - 2008 Nokia Corporation
11 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
17 #define pr_fmt(fmt) "clock: " fmt
36 /* clock disable operations are not passed on to hardware during boot */
46 unsigned long freq; in clk_rate_table_build() local
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
[all …]
/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Dtimer-fsl-ftm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 if (priv->big_endian) in ftm_readl()
42 if (priv->big_endian) in ftm_writel()
52 /* select and enable counter clock source */ in ftm_counter_enable()
55 val |= priv->ps | FTM_SC_CLK(1); in ftm_counter_enable()
63 /* disable counter clock source */ in ftm_counter_disable()
108 return ftm_readl(priv->clksrc_base + FTM_CNT); in ftm_read_sched_clock()
119 * a, the counter source clock is diabled. in ftm_set_next_event()
121 ftm_counter_disable(priv->clkevt_base); in ftm_set_next_event()
124 ftm_reset_counter(priv->clkevt_base); in ftm_set_next_event()
[all …]
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dpicoxcell-pc3x3.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 #address-cells = <1>;
9 #size-cells = <1>;
12 #address-cells = <0>;
13 #size-cells = <0>;
16 compatible = "arm,arm1176jz-s";
18 cpu-clock = <&arm_clk>, "cpu";
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_afmt.c34 /* Clock N CTS N CTS N CTS */
51 static void amdgpu_afmt_calc_cts(uint32_t clock, int *CTS, int *N, int freq) in amdgpu_afmt_calc_cts() argument
57 n = 128 * freq; in amdgpu_afmt_calc_cts()
58 cts = clock * 1000; in amdgpu_afmt_calc_cts()
67 * The optimal N is 128*freq/1000. Calculate the closest larger in amdgpu_afmt_calc_cts()
70 mul = ((128*freq/1000) + (n-1))/n; in amdgpu_afmt_calc_cts()
76 if (n < (128*freq/1500)) in amdgpu_afmt_calc_cts()
78 if (n > (128*freq/300)) in amdgpu_afmt_calc_cts()
85 *N, *CTS, freq); in amdgpu_afmt_calc_cts()
88 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock) in amdgpu_afmt_acr() argument
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/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/armv7/
H A Dclock.c2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
10 * SPDX-License-Identifier: GPL-2.0+
32 return gd->arch.main_clk_rate_hz; in at91_css_to_rate()
34 return gd->arch.plla_rate_hz; in at91_css_to_rate()
40 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
47 freq /= div; in at91_pll_rate()
48 freq *= mul + 1; in at91_pll_rate()
50 freq = 0; in at91_pll_rate()
53 return freq; in at91_pll_rate()
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/OK3568_Linux_fs/kernel/drivers/net/can/cc770/
H A Dcc770_platform.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * in your board-specific code:
29 * interrupt-parent = <&mpic>;
30 * bosch,external-clock-frequency = <16000000>;
53 MODULE_DESCRIPTION("Socket-CAN driver for CC770 on the platform bus");
61 return ioread8(priv->reg_base + reg); in cc770_platform_read_reg()
67 iowrite8(val, priv->reg_base + reg); in cc770_platform_write_reg()
73 struct device_node *np = pdev->dev.of_node; in cc770_get_of_node_data()
78 prop = of_get_property(np, "bosch,external-clock-frequency", in cc770_get_of_node_data()
84 priv->can.clock.freq = clkext; in cc770_get_of_node_data()
[all …]
/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Darmada-8k-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
34 unsigned int freq[ARRAY_SIZE(opps_div)]; member
37 /* If the CPUs share the same clock, then they are in the same cluster. */
55 pr_warn("Cannot get clock for CPU %d\n", cpu); in armada_8k_get_sharing_cpus()
70 unsigned int freq; in armada_8k_add_opp() local
76 dev_err(cpu_dev, "Failed to get clock rate for this CPU\n"); in armada_8k_add_opp()
77 return -EINVAL; in armada_8k_add_opp()
83 freq = cur_frequency / opps_div[i]; in armada_8k_add_opp()
85 ret = dev_pm_opp_add(cpu_dev, freq, 0); in armada_8k_add_opp()
89 freq_tables[opps_index].freq[i] = freq; in armada_8k_add_opp()
[all …]
H A Ds3c24xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
62 cfg->freq.fclk = fclk = clk_get_rate(clk_fclk); in s3c_cpufreq_getcur()
63 cfg->freq.hclk = hclk = clk_get_rate(clk_hclk); in s3c_cpufreq_getcur()
64 cfg->freq.pclk = pclk = clk_get_rate(clk_pclk); in s3c_cpufreq_getcur()
65 cfg->freq.armclk = armclk = clk_get_rate(clk_arm); in s3c_cpufreq_getcur()
67 cfg->pll.driver_data = s3c24xx_read_mpllcon(); in s3c_cpufreq_getcur()
68 cfg->pll.frequency = fclk; in s3c_cpufreq_getcur()
[all …]
H A Ds3c2412-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <linux/soc/samsung/s3c-cpufreq-core.h>
23 #include <linux/soc/samsung/s3c-pm.h>
41 /* our clock resources. */
55 fclk = cfg->freq.fclk; in s3c2412_cpufreq_calcdivs()
56 armclk = cfg->freq.armclk; in s3c2412_cpufreq_calcdivs()
57 hclk_max = cfg->max.hclk; in s3c2412_cpufreq_calcdivs()
68 __func__, cfg->freq.fclk, cfg->freq.armclk, in s3c2412_cpufreq_calcdivs()
69 cfg->freq.hclk, cfg->freq.pclk); in s3c2412_cpufreq_calcdivs()
78 cfg->divs.arm_divisor = armdiv; in s3c2412_cpufreq_calcdivs()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_devfreq.c1 // SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
4 * (C) COPYRIGHT 2014-2022 ARM Limited. All rights reserved.
18 * http://www.gnu.org/licenses/gpl-2.0.html.
20 * SPDX-License-Identifier: GPL-2.0
31 #include <linux/clk-provider.h>
56 * get_voltage() - Get the voltage value corresponding to the nominal frequency
59 * @freq: Nominal frequency in Hz passed by devfreq.
62 * "operating-points-v2-mali", is not present in the devicetree for GPU device.
66 static unsigned long get_voltage(struct kbase_device *kbdev, unsigned long freq) in get_voltage() argument
75 opp = dev_pm_opp_find_freq_exact(kbdev->dev, freq, true); in get_voltage()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c2 * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
6 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8 * SPDX-License-Identifier: GPL-2.0+
31 return gd->arch.main_clk_rate_hz; in at91_css_to_rate()
33 return gd->arch.plla_rate_hz; in at91_css_to_rate()
35 return gd->arch.pllb_rate_hz; in at91_css_to_rate()
80 diff1 = out_freq - input * mul1; in at91_pll_calc()
82 diff1 = -diff1; in at91_pll_calc()
93 return ret | ((mul - 1) << 16) | div; in at91_pll_calc()
99 static u32 at91_pll_rate(u32 freq, u32 reg) in at91_pll_rate() argument
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/hisilicon/
H A Dclk-hi6220-stub.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Hi6220 stub clock driver
11 #include <linux/clk-provider.h>
69 unsigned int freq; in hi6220_acpu_get_freq() local
71 regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq); in hi6220_acpu_get_freq()
72 return freq; in hi6220_acpu_get_freq()
76 unsigned int freq) in hi6220_acpu_set_freq() argument
81 regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq); in hi6220_acpu_set_freq()
89 mbox_send_message(stub_clk->mbox, &data); in hi6220_acpu_set_freq()
94 unsigned int freq) in hi6220_acpu_round_freq() argument
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/sound/
H A Datmel-pdmic.txt4 - compatible
5 Should be "atmel,sama5d2-pdmic".
6 - reg
8 - interrupts
10 - dmas
11 One DMA specifiers as described in atmel-dma.txt and dma.txt files.
12 - dma-names
14 - clock-names
16 - "pclk" peripheral clock
17 - "gclk" generated clock
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dclock.c2 * Freescale i.MX23/i.MX28 clock setup code
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/clock.h>
17 #include <asm/arch/imx-regs.h>
45 clkctrl = readl(&clkctrl_regs->hw_clkctrl_cpu); in mxs_get_pclk()
53 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); in mxs_get_pclk()
63 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); in mxs_get_pclk()
77 clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus); in mxs_get_hclk()
95 clkseq = readl(&clkctrl_regs->hw_clkctrl_clkseq); in mxs_get_emiclk()
96 clkctrl = readl(&clkctrl_regs->hw_clkctrl_emi); in mxs_get_emiclk()
[all …]

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