2  * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
6  * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
8  * SPDX-License-Identifier:	GPL-2.0+
31 		return gd->arch.main_clk_rate_hz;  in at91_css_to_rate()
33 		return gd->arch.plla_rate_hz;  in at91_css_to_rate()
35 		return gd->arch.pllb_rate_hz;  in at91_css_to_rate()
80 		diff1 = out_freq - input * mul1;  in at91_pll_calc()
82 			diff1 = -diff1;  in at91_pll_calc()
93 	return ret | ((mul - 1) << 16) | div;  in at91_pll_calc()
99 static u32 at91_pll_rate(u32 freq, u32 reg)  in at91_pll_rate()  argument
106 		freq /= div;  in at91_pll_rate()
107 		freq *= mul + 1;  in at91_pll_rate()
109 		freq = 0;  in at91_pll_rate()
111 	return freq;  in at91_pll_rate()
116 	unsigned freq, mckr;  in at91_clock_init()  local
124 	 * of the main clock.  in at91_clock_init()
128 			tmp = readl(&pmc->mcfr);  in at91_clock_init()
134 	gd->arch.main_clk_rate_hz = main_clock;  in at91_clock_init()
137 	gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));  in at91_clock_init()
141 	 * USB clock init:  choose 48 MHz PLLB value,  in at91_clock_init()
142 	 * disable 48MHz clock during usb peripheral suspend.  in at91_clock_init()
146 	gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |  in at91_clock_init()
148 	gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,  in at91_clock_init()
149 					      gd->arch.at91_pllb_usb_init);  in at91_clock_init()
156 	mckr = readl(&pmc->mckr);  in at91_clock_init()
160 	gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));  in at91_clock_init()
162 	gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);  in at91_clock_init()
163 	freq = gd->arch.mck_rate_hz;  in at91_clock_init()
167 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));  in at91_clock_init()
169 	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */  in at91_clock_init()
174 	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?  in at91_clock_init()
175 		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;  in at91_clock_init()
177 		freq /= 2;			/* processor clock division */  in at91_clock_init()
186 	gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==  in at91_clock_init()
188 		? freq / 3  in at91_clock_init()
189 		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));  in at91_clock_init()
191 	gd->arch.mck_rate_hz = freq /  in at91_clock_init()
194 	gd->arch.cpu_clk_rate_hz = freq;  in at91_clock_init()
207 	writel(pllar, &pmc->pllar);  in at91_plla_init()
208 	while (!(readl(&pmc->sr) & AT91_PMC_LOCKA))  in at91_plla_init()
215 	writel(pllbr, &pmc->pllbr);  in at91_pllb_init()
216 	while (!(readl(&pmc->sr) & AT91_PMC_LOCKB))  in at91_pllb_init()
225 	tmp = readl(&pmc->mckr);  in at91_mck_init()
228 	writel(tmp, &pmc->mckr);  in at91_mck_init()
229 	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))  in at91_mck_init()
232 	tmp = readl(&pmc->mckr);  in at91_mck_init()
235 	writel(tmp, &pmc->mckr);  in at91_mck_init()
236 	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))  in at91_mck_init()
239 	tmp = readl(&pmc->mckr);  in at91_mck_init()
242 	writel(tmp, &pmc->mckr);  in at91_mck_init()
243 	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))  in at91_mck_init()
246 	tmp = readl(&pmc->mckr);  in at91_mck_init()
249 	writel(tmp, &pmc->mckr);  in at91_mck_init()
250 	while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY))  in at91_mck_init()
260 	writel(pllbr, &pmc->pllbr);  in at91_pllb_clk_enable()
261 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {  in at91_pllb_clk_enable()
263 		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {  in at91_pllb_clk_enable()
265 			return -1;  in at91_pllb_clk_enable()
278 	writel(0, &pmc->pllbr);  in at91_pllb_clk_disable()
279 	while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {  in at91_pllb_clk_disable()
281 		if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {  in at91_pllb_clk_disable()
283 			return -1;  in at91_pllb_clk_disable()