Lines Matching +full:clock +full:- +full:freq
7 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
31 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); in get_clocks()
33 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); in get_clocks()
35 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); in get_clocks()
82 /* disable the clock gate first */ in enable_usboh3_clk()
92 /* enable the clock gate */ in enable_usboh3_clk()
116 reg = readl(&ccm_anatop->pll_arm); in decode_pll()
130 reg = readl(&ccm_anatop->pll_480); in decode_pll()
145 reg = readl(&ccm_anatop->pll_enet); in decode_pll()
156 reg = readl(&ccm_anatop->pll_ddr); in decode_pll()
161 num = ccm_anatop->pll_ddr_num; in decode_pll()
162 denom = ccm_anatop->pll_ddr_denom; in decode_pll()
185 u32 freq, div, frac; in mxc_get_pll_sys_derive() local
189 reg = readl(&ccm_anatop->pll_480); in mxc_get_pll_sys_derive()
190 freq = decode_pll(PLL_SYS, MXC_HCLK); in mxc_get_pll_sys_derive()
197 return freq; in mxc_get_pll_sys_derive()
202 return freq / 2; in mxc_get_pll_sys_derive()
207 return freq / 4; in mxc_get_pll_sys_derive()
209 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
218 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
224 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
233 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
239 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
248 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
254 reg = readl(&ccm_anatop->pfd_480a); in mxc_get_pll_sys_derive()
261 reg = readl(&ccm_anatop->pfd_480b); in mxc_get_pll_sys_derive()
268 reg = readl(&ccm_anatop->pfd_480b); in mxc_get_pll_sys_derive()
275 reg = readl(&ccm_anatop->pfd_480b); in mxc_get_pll_sys_derive()
282 reg = readl(&ccm_anatop->pfd_480b); in mxc_get_pll_sys_derive()
289 printf("Error derived pll_sys clock %d\n", derive); in mxc_get_pll_sys_derive()
293 return ((freq / frac) * 18) / div; in mxc_get_pll_sys_derive()
298 u32 freq, reg; in mxc_get_pll_enet_derive() local
300 freq = decode_pll(PLL_ENET, MXC_HCLK); in mxc_get_pll_enet_derive()
301 reg = readl(&ccm_anatop->pll_enet); in mxc_get_pll_enet_derive()
306 return freq / 2; in mxc_get_pll_enet_derive()
310 return freq / 4; in mxc_get_pll_enet_derive()
314 return freq / 8; in mxc_get_pll_enet_derive()
318 return freq / 10; in mxc_get_pll_enet_derive()
322 return freq / 20; in mxc_get_pll_enet_derive()
326 return freq / 25; in mxc_get_pll_enet_derive()
330 return freq / 40; in mxc_get_pll_enet_derive()
333 printf("Error derived pll_enet clock %d\n", derive); in mxc_get_pll_enet_derive()
342 u32 freq, reg; in mxc_get_pll_ddr_derive() local
344 freq = decode_pll(PLL_DDR, MXC_HCLK); in mxc_get_pll_ddr_derive()
345 reg = readl(&ccm_anatop->pll_ddr); in mxc_get_pll_ddr_derive()
349 return freq; in mxc_get_pll_ddr_derive()
352 return freq / 2; in mxc_get_pll_ddr_derive()
355 printf("Error derived pll_ddr clock %d\n", derive); in mxc_get_pll_ddr_derive()
474 u32 reg, freq; in get_ddrc_clk() local
477 reg = readl(&ccm_reg->root[DRAM_CLK_ROOT].target_root); in get_ddrc_clk()
480 freq = get_root_clk(DRAM_ALT_CLK_ROOT); in get_ddrc_clk()
483 freq = mxc_get_pll_derive(PLL_DDR, PLL_DRAM_MAIN_1066M_CLK); in get_ddrc_clk()
487 return freq / (post_div + 1) / 2; in get_ddrc_clk()
524 /* i2c_num can be 0 - 3 */
530 return -EINVAL; in enable_i2c_clk()
535 /* Set i2c root clock to PLL_SYS_MAIN_120M_CLK */ in enable_i2c_clk()
556 /* disable the clock gate first */ in init_clk_esdhc()
577 /* enable the clock gate */ in init_clk_esdhc()
587 /* disable the clock gate first */ in init_clk_uart()
632 /* enable the clock gate */ in init_clk_uart()
646 /* disable the clock gate first */ in init_clk_weim()
655 /* enable the clock gate */ in init_clk_weim()
663 /* disable the clock gate first */ in init_clk_ecspi()
690 /* enable the clock gate */ in init_clk_ecspi()
701 /* disable the clock gate first */ in init_clk_wdog()
713 /* enable the clock gate */ in init_clk_wdog()
725 /* disable the clock gate first */ in init_clk_epdc()
734 /* enable the clock gate */ in init_clk_epdc()
744 reg = readl(&ccm_anatop->pll_enet); in enable_pll_enet()
748 writel(reg, &ccm_anatop->pll_enet); in enable_pll_enet()
750 while (timeout--) { in enable_pll_enet()
751 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) in enable_pll_enet()
758 return -ETIME; in enable_pll_enet()
763 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr); in enable_pll_enet()
772 &ccm_anatop->pll_enet_set); in enable_pll_enet()
792 &ccm_anatop->pll_video_clr); in enable_pll_video()
800 &ccm_anatop->pll_video_set); in enable_pll_video()
806 &ccm_anatop->pll_video_set); in enable_pll_video()
812 &ccm_anatop->pll_video_set); in enable_pll_video()
818 &ccm_anatop->pll_video_set); in enable_pll_video()
825 &ccm_anatop->pll_video_set); in enable_pll_video()
830 &ccm_anatop->pll_video_num); in enable_pll_video()
833 &ccm_anatop->pll_video_denom); in enable_pll_video()
839 reg = readl(&ccm_anatop->pll_video); in enable_pll_video()
843 &ccm_anatop->pll_video_set); in enable_pll_video()
857 /* disable the clock gate first */ in set_clk_qspi()
866 /* enable the clock gate */ in set_clk_qspi()
876 /* disable the clock gate first */ in set_clk_nand()
886 /* enable the clock gate */ in set_clk_nand()
892 void mxs_set_lcdclk(uint32_t base_addr, uint32_t freq) in mxs_set_lcdclk() argument
902 debug("mxs_set_lcdclk, freq = %d\n", freq); in mxs_set_lcdclk()
906 temp = (freq * 8 * 8); in mxs_set_lcdclk()
911 freq = (freq * (1 << i)); in mxs_set_lcdclk()
917 printf("Fail to set rate to %dkhz", freq); in mxs_set_lcdclk()
924 temp = freq * i * j; in mxs_set_lcdclk()
937 printf("Fail to set rate to %dkhz", freq); in mxs_set_lcdclk()
945 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
951 CLK_ROOT_PRE_DIV((pred - 1)) | CLK_ROOT_POST_DIV((postd - 1)); in mxs_set_lcdclk()
964 /* disable the clock first */ in set_clk_enet()
982 return -EINVAL; in set_clk_enet()
989 /* set enet axi clock 196M: 392/2 */ in set_clk_enet()
1022 /* enable clock */ in set_clk_enet()
1030 /* Configure PLL/PFD freq */
1034 * In u-boot, we have to: in clock_init()
1035 * 1. Configure PFD3- PFD7 for freq we needed in u-boot in clock_init()
1036 * 2. Set clock root for peripherals (ip channel) used in u-boot but without set rate in clock_init()
1038 * 3. Other peripherals with set clock rate interface does not be set in this function. in clock_init()
1046 reg = readl(&ccm_anatop->pfd_480b); in clock_init()
1052 writel(reg, &ccm_anatop->pfd_480b); in clock_init()
1104 u32 freq; in do_mx7_showclocks() local
1105 freq = decode_pll(PLL_CORE, MXC_HCLK); in do_mx7_showclocks()
1106 printf("PLL_CORE %8d MHz\n", freq / 1000000); in do_mx7_showclocks()
1107 freq = decode_pll(PLL_SYS, MXC_HCLK); in do_mx7_showclocks()
1108 printf("PLL_SYS %8d MHz\n", freq / 1000000); in do_mx7_showclocks()
1109 freq = decode_pll(PLL_ENET, MXC_HCLK); in do_mx7_showclocks()
1110 printf("PLL_NET %8d MHz\n", freq / 1000000); in do_mx7_showclocks()