Lines Matching +full:clock +full:- +full:freq
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/clock.h>
70 ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
78 clrsetbits_le32(&mxc_ccm->cscmr1, in set_usboh3_clk()
81 clrsetbits_le32(&mxc_ccm->cscdr1, in set_usboh3_clk()
92 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usboh3_clk()
108 return -EINVAL; in enable_i2c_clk()
112 setbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
114 clrbits_le32(&mxc_ccm->CCGR1, mask); in enable_i2c_clk()
121 clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL); in set_usb_phy_clk()
129 clrsetbits_le32(&mxc_ccm->CCGR2, in enable_usb_phy1_clk()
136 /* i.MX51 has a single USB PHY clock, so do nothing here. */ in enable_usb_phy2_clk()
143 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy1_clk()
152 clrsetbits_le32(&mxc_ccm->CCGR4, in enable_usb_phy2_clk()
167 ctrl = readl(&pll->ctrl); in decode_pll()
170 mfn = readl(&pll->hfs_mfn); in decode_pll()
171 mfd = readl(&pll->hfs_mfd); in decode_pll()
172 op = readl(&pll->hfs_op); in decode_pll()
174 mfn = readl(&pll->mfn); in decode_pll()
175 mfd = readl(&pll->mfd); in decode_pll()
176 op = readl(&pll->op); in decode_pll()
191 mfn_abs = -mfn; in decode_pll()
205 ret -= temp; in decode_pll()
214 * This function returns the Frequency Pre-Multiplier clock.
219 u32 ccr = readl(&mxc_ccm->ccr); in get_fpm()
231 * This function returns the low power audio clock.
236 u32 ccsr = readl(&mxc_ccm->ccsr); in get_lp_apm()
255 u32 reg, freq; in get_mcu_main_clk() local
257 reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr)); in get_mcu_main_clk()
258 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
259 return freq / (reg + 1); in get_mcu_main_clk()
263 * Get the rate of peripheral's root clock.
269 reg = readl(&mxc_ccm->cbcdr); in get_periph_clk()
272 reg = readl(&mxc_ccm->cbcmr); in get_periph_clk()
287 * Get the rate of ipg clock.
291 uint32_t freq, reg, div; in get_ipg_clk() local
293 freq = get_ahb_clk(); in get_ipg_clk()
295 reg = readl(&mxc_ccm->cbcdr); in get_ipg_clk()
298 return freq / div; in get_ipg_clk()
302 * Get the rate of ipg_per clock.
306 u32 freq, pred1, pred2, podf; in get_ipg_per_clk() local
308 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) in get_ipg_per_clk()
311 if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL) in get_ipg_per_clk()
312 freq = get_lp_apm(); in get_ipg_per_clk()
314 freq = get_periph_clk(); in get_ipg_per_clk()
315 podf = readl(&mxc_ccm->cbcdr); in get_ipg_per_clk()
319 return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); in get_ipg_per_clk()
322 /* Get the output clock rate of a standard PLL MUX for peripherals. */
325 u32 freq = 0; in get_standard_pll_sel_clk() local
329 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
332 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
335 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
338 freq = get_lp_apm(); in get_standard_pll_sel_clk()
342 return freq; in get_standard_pll_sel_clk()
350 unsigned int clk_sel, freq, reg, pred, podf; in get_uart_clk() local
352 reg = readl(&mxc_ccm->cscmr1); in get_uart_clk()
354 freq = get_standard_pll_sel_clk(clk_sel); in get_uart_clk()
356 reg = readl(&mxc_ccm->cscdr1); in get_uart_clk()
359 freq /= (pred + 1) * (podf + 1); in get_uart_clk()
361 return freq; in get_uart_clk()
365 * get cspi clock rate.
369 u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq; in imx_get_cspiclk() local
370 u32 cscmr1 = readl(&mxc_ccm->cscmr1); in imx_get_cspiclk()
371 u32 cscdr2 = readl(&mxc_ccm->cscdr2); in imx_get_cspiclk()
376 freq = get_standard_pll_sel_clk(clk_sel); in imx_get_cspiclk()
377 ret_val = freq / ((pre_pdf + 1) * (pdf + 1)); in imx_get_cspiclk()
382 * get esdhc clock rate.
386 u32 clk_sel = 0, pred = 0, podf = 0, freq = 0; in get_esdhc_clk() local
387 u32 cscmr1 = readl(&mxc_ccm->cscmr1); in get_esdhc_clk()
388 u32 cscdr1 = readl(&mxc_ccm->cscdr1); in get_esdhc_clk()
415 freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1)); in get_esdhc_clk()
416 return freq; in get_esdhc_clk()
421 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_axi_a_clk()
429 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_axi_b_clk()
437 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_emi_slow_clk()
450 u32 cbcmr = readl(&mxc_ccm->cbcmr); in get_ddr_clk()
453 u32 cbcdr = readl(&mxc_ccm->cbcdr); in get_ddr_clk()
519 return -EINVAL; in mxc_get_clock()
541 m -= n; in gcd()
547 * This is to calculate various parameters based on reference clock and
548 * targeted clock based on the equation:
559 * Make sure targeted freq is in the valid range. in calc_pll_params()
564 printf("Targeted peripheral clock should be" in calc_pll_params()
565 "within [%d - %d]\n", in calc_pll_params()
568 return -EINVAL; in calc_pll_params()
579 return -EINVAL; in calc_pll_params()
587 return -EINVAL; in calc_pll_params()
595 * mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; in calc_pll_params()
599 t1 -= n_ref * mfi; in calc_pll_params()
608 pll->pd = (u32)pd; in calc_pll_params()
609 pll->mfi = (u32)mfi; in calc_pll_params()
611 pll->mfn = (u32)mfn; in calc_pll_params()
613 pll->mfd = (u32)mfd; in calc_pll_params()
626 (v - 1); \
631 writel(0x1232, &pll->ctrl); \
632 writel(0x2, &pll->config); \
633 writel((((pd) - 1) << 0) | ((fi) << 4), \
634 &pll->op); \
635 writel(fn, &(pll->mfn)); \
636 writel((fd) - 1, &pll->mfd); \
637 writel((((pd) - 1) << 0) | ((fi) << 4), \
638 &pll->hfs_op); \
639 writel(fn, &pll->hfs_mfn); \
640 writel((fd) - 1, &pll->hfs_mfd); \
641 writel(0x1232, &pll->ctrl); \
642 while (!readl(&pll->ctrl) & 0x1) \
648 u32 ccsr = readl(&mxc_ccm->ccsr); in config_pll_clk()
653 /* Switch ARM to PLL2 clock */ in config_pll_clk()
655 &mxc_ccm->ccsr); in config_pll_clk()
656 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
657 pll_param->mfi, pll_param->mfn, in config_pll_clk()
658 pll_param->mfd); in config_pll_clk()
661 &mxc_ccm->ccsr); in config_pll_clk()
664 /* Switch to pll2 bypass clock */ in config_pll_clk()
666 &mxc_ccm->ccsr); in config_pll_clk()
667 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
668 pll_param->mfi, pll_param->mfn, in config_pll_clk()
669 pll_param->mfd); in config_pll_clk()
672 &mxc_ccm->ccsr); in config_pll_clk()
675 /* Switch to pll3 bypass clock */ in config_pll_clk()
677 &mxc_ccm->ccsr); in config_pll_clk()
678 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
679 pll_param->mfi, pll_param->mfn, in config_pll_clk()
680 pll_param->mfd); in config_pll_clk()
683 &mxc_ccm->ccsr); in config_pll_clk()
687 /* Switch to pll4 bypass clock */ in config_pll_clk()
689 &mxc_ccm->ccsr); in config_pll_clk()
690 CHANGE_PLL_SETTINGS(pll, pll_param->pd, in config_pll_clk()
691 pll_param->mfi, pll_param->mfn, in config_pll_clk()
692 pll_param->mfd); in config_pll_clk()
695 &mxc_ccm->ccsr); in config_pll_clk()
699 return -EINVAL; in config_pll_clk()
705 /* Config CPU clock */
706 static int config_core_clk(u32 ref, u32 freq) in config_core_clk() argument
714 ret = calc_pll_params(ref, freq, &pll_param); in config_core_clk()
729 return -EINVAL; in config_nfc_clk()
735 clrsetbits_le32(&mxc_ccm->cbcdr, in config_nfc_clk()
737 MXC_CCM_CBCDR_NFC_PODF(div - 1)); in config_nfc_clk()
738 while (readl(&mxc_ccm->cdhipr) != 0) in config_nfc_clk()
747 clrsetbits_le32(&mxc_ccm->CCGR5, in enable_nfc_clk()
756 setbits_le32(&mxc_ccm->cgpr, in enable_efuse_prog_supply()
759 clrbits_le32(&mxc_ccm->cgpr, in enable_efuse_prog_supply()
765 static int config_periph_clk(u32 ref, u32 freq) in config_periph_clk() argument
772 if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { in config_periph_clk()
773 ret = calc_pll_params(ref, freq, &pll_param); in config_periph_clk()
780 readl(&mxc_ccm->cbcmr))) { in config_periph_clk()
788 return -EINVAL; in config_periph_clk()
799 u32 cbcmr = readl(&mxc_ccm->cbcmr); in config_ddr_clk()
802 printf("Warning:DDR clock should not exceed %d MHz\n", in config_ddr_clk()
808 /* Find DDR clock input */ in config_ddr_clk()
824 return -EINVAL; in config_ddr_clk()
834 clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift); in config_ddr_clk()
835 while (readl(&mxc_ccm->cdhipr) != 0) in config_ddr_clk()
837 writel(0x0, &mxc_ccm->ccdr); in config_ddr_clk()
843 * This function assumes the expected core clock has to be changed by
845 * it is. So it assumes the PLL output freq is the same as the expected
846 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
850 * on the targeted PLL and reference input clock to the PLL. Lastly,
852 * Note 1) There is no value checking for the passed-in divider values
854 * 2) Also adjust the NFC divider such that the NFC clock doesn't
856 * 3) IPU HSP clock is independent of AHB clock. Even it can go up to
862 int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) in mxc_set_clock() argument
864 freq *= SZ_DEC_1M; in mxc_set_clock()
868 if (config_core_clk(ref, freq)) in mxc_set_clock()
869 return -EINVAL; in mxc_set_clock()
872 if (config_periph_clk(ref, freq)) in mxc_set_clock()
873 return -EINVAL; in mxc_set_clock()
876 if (config_ddr_clk(freq)) in mxc_set_clock()
877 return -EINVAL; in mxc_set_clock()
880 if (config_nfc_clk(freq)) in mxc_set_clock()
881 return -EINVAL; in mxc_set_clock()
884 printf("Warning:Unsupported or invalid clock type\n"); in mxc_set_clock()
892 * The clock for the external interface can be set to use internal clock
898 * '00' - 100MHz (External)
899 * '01' - 50MHz (External)
900 * '10' - 120MHz, internal (USB PHY)
901 * '11' - Reserved
919 u32 freq; in do_mx5_showclocks() local
921 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
922 printf("PLL1 %8d MHz\n", freq / 1000000); in do_mx5_showclocks()
923 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
924 printf("PLL2 %8d MHz\n", freq / 1000000); in do_mx5_showclocks()
925 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in do_mx5_showclocks()
926 printf("PLL3 %8d MHz\n", freq / 1000000); in do_mx5_showclocks()
928 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()
929 printf("PLL4 %8d MHz\n", freq / 1000000); in do_mx5_showclocks()