1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Hi6220 stub clock driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015 Hisilicon Limited.
6*4882a593Smuzhiyun * Copyright (c) 2015 Linaro Limited.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Leo Yan <leo.yan@linaro.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/clk-provider.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/kernel.h>
14*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
15*4882a593Smuzhiyun #include <linux/mailbox_client.h>
16*4882a593Smuzhiyun #include <linux/of.h>
17*4882a593Smuzhiyun #include <linux/of_device.h>
18*4882a593Smuzhiyun #include <linux/regmap.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Stub clocks id */
21*4882a593Smuzhiyun #define HI6220_STUB_ACPU0 0
22*4882a593Smuzhiyun #define HI6220_STUB_ACPU1 1
23*4882a593Smuzhiyun #define HI6220_STUB_GPU 2
24*4882a593Smuzhiyun #define HI6220_STUB_DDR 5
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* Mailbox message */
27*4882a593Smuzhiyun #define HI6220_MBOX_MSG_LEN 8
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define HI6220_MBOX_FREQ 0xA
30*4882a593Smuzhiyun #define HI6220_MBOX_CMD_SET 0x3
31*4882a593Smuzhiyun #define HI6220_MBOX_OBJ_AP 0x0
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* CPU dynamic frequency scaling */
34*4882a593Smuzhiyun #define ACPU_DFS_FREQ_MAX 0x1724
35*4882a593Smuzhiyun #define ACPU_DFS_CUR_FREQ 0x17CC
36*4882a593Smuzhiyun #define ACPU_DFS_FLAG 0x1B30
37*4882a593Smuzhiyun #define ACPU_DFS_FREQ_REQ 0x1B34
38*4882a593Smuzhiyun #define ACPU_DFS_FREQ_LMT 0x1B38
39*4882a593Smuzhiyun #define ACPU_DFS_LOCK_FLAG 0xAEAEAEAE
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define to_stub_clk(hw) container_of(hw, struct hi6220_stub_clk, hw)
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct hi6220_stub_clk {
44*4882a593Smuzhiyun u32 id;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct device *dev;
47*4882a593Smuzhiyun struct clk_hw hw;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct regmap *dfs_map;
50*4882a593Smuzhiyun struct mbox_client cl;
51*4882a593Smuzhiyun struct mbox_chan *mbox;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct hi6220_mbox_msg {
55*4882a593Smuzhiyun unsigned char type;
56*4882a593Smuzhiyun unsigned char cmd;
57*4882a593Smuzhiyun unsigned char obj;
58*4882a593Smuzhiyun unsigned char src;
59*4882a593Smuzhiyun unsigned char para[4];
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun union hi6220_mbox_data {
63*4882a593Smuzhiyun unsigned int data[HI6220_MBOX_MSG_LEN];
64*4882a593Smuzhiyun struct hi6220_mbox_msg msg;
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
hi6220_acpu_get_freq(struct hi6220_stub_clk * stub_clk)67*4882a593Smuzhiyun static unsigned int hi6220_acpu_get_freq(struct hi6220_stub_clk *stub_clk)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun unsigned int freq;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun regmap_read(stub_clk->dfs_map, ACPU_DFS_CUR_FREQ, &freq);
72*4882a593Smuzhiyun return freq;
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun
hi6220_acpu_set_freq(struct hi6220_stub_clk * stub_clk,unsigned int freq)75*4882a593Smuzhiyun static int hi6220_acpu_set_freq(struct hi6220_stub_clk *stub_clk,
76*4882a593Smuzhiyun unsigned int freq)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun union hi6220_mbox_data data;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun /* set the frequency in sram */
81*4882a593Smuzhiyun regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, freq);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* compound mailbox message */
84*4882a593Smuzhiyun data.msg.type = HI6220_MBOX_FREQ;
85*4882a593Smuzhiyun data.msg.cmd = HI6220_MBOX_CMD_SET;
86*4882a593Smuzhiyun data.msg.obj = HI6220_MBOX_OBJ_AP;
87*4882a593Smuzhiyun data.msg.src = HI6220_MBOX_OBJ_AP;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun mbox_send_message(stub_clk->mbox, &data);
90*4882a593Smuzhiyun return 0;
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun
hi6220_acpu_round_freq(struct hi6220_stub_clk * stub_clk,unsigned int freq)93*4882a593Smuzhiyun static int hi6220_acpu_round_freq(struct hi6220_stub_clk *stub_clk,
94*4882a593Smuzhiyun unsigned int freq)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun unsigned int limit_flag, limit_freq = UINT_MAX;
97*4882a593Smuzhiyun unsigned int max_freq;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* check the constrained frequency */
100*4882a593Smuzhiyun regmap_read(stub_clk->dfs_map, ACPU_DFS_FLAG, &limit_flag);
101*4882a593Smuzhiyun if (limit_flag == ACPU_DFS_LOCK_FLAG)
102*4882a593Smuzhiyun regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, &limit_freq);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* check the supported maximum frequency */
105*4882a593Smuzhiyun regmap_read(stub_clk->dfs_map, ACPU_DFS_FREQ_MAX, &max_freq);
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* calculate the real maximum frequency */
108*4882a593Smuzhiyun max_freq = min(max_freq, limit_freq);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun if (WARN_ON(freq > max_freq))
111*4882a593Smuzhiyun freq = max_freq;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return freq;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
hi6220_stub_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)116*4882a593Smuzhiyun static unsigned long hi6220_stub_clk_recalc_rate(struct clk_hw *hw,
117*4882a593Smuzhiyun unsigned long parent_rate)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun u32 rate = 0;
120*4882a593Smuzhiyun struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun switch (stub_clk->id) {
123*4882a593Smuzhiyun case HI6220_STUB_ACPU0:
124*4882a593Smuzhiyun rate = hi6220_acpu_get_freq(stub_clk);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun /* convert from kHz to Hz */
127*4882a593Smuzhiyun rate *= 1000;
128*4882a593Smuzhiyun break;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun default:
131*4882a593Smuzhiyun dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
132*4882a593Smuzhiyun __func__, stub_clk->id);
133*4882a593Smuzhiyun break;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return rate;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
hi6220_stub_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)139*4882a593Smuzhiyun static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
140*4882a593Smuzhiyun unsigned long parent_rate)
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
143*4882a593Smuzhiyun unsigned long new_rate = rate / 1000; /* kHz */
144*4882a593Smuzhiyun int ret = 0;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun switch (stub_clk->id) {
147*4882a593Smuzhiyun case HI6220_STUB_ACPU0:
148*4882a593Smuzhiyun ret = hi6220_acpu_set_freq(stub_clk, new_rate);
149*4882a593Smuzhiyun if (ret < 0)
150*4882a593Smuzhiyun return ret;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun break;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun default:
155*4882a593Smuzhiyun dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
156*4882a593Smuzhiyun __func__, stub_clk->id);
157*4882a593Smuzhiyun break;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun pr_debug("%s: set rate=%ldkHz\n", __func__, new_rate);
161*4882a593Smuzhiyun return ret;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
hi6220_stub_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)164*4882a593Smuzhiyun static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
165*4882a593Smuzhiyun unsigned long *parent_rate)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
168*4882a593Smuzhiyun unsigned long new_rate = rate / 1000; /* kHz */
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun switch (stub_clk->id) {
171*4882a593Smuzhiyun case HI6220_STUB_ACPU0:
172*4882a593Smuzhiyun new_rate = hi6220_acpu_round_freq(stub_clk, new_rate);
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* convert from kHz to Hz */
175*4882a593Smuzhiyun new_rate *= 1000;
176*4882a593Smuzhiyun break;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun default:
179*4882a593Smuzhiyun dev_err(stub_clk->dev, "%s: un-supported clock id %d\n",
180*4882a593Smuzhiyun __func__, stub_clk->id);
181*4882a593Smuzhiyun break;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return new_rate;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static const struct clk_ops hi6220_stub_clk_ops = {
188*4882a593Smuzhiyun .recalc_rate = hi6220_stub_clk_recalc_rate,
189*4882a593Smuzhiyun .round_rate = hi6220_stub_clk_round_rate,
190*4882a593Smuzhiyun .set_rate = hi6220_stub_clk_set_rate,
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
hi6220_stub_clk_probe(struct platform_device * pdev)193*4882a593Smuzhiyun static int hi6220_stub_clk_probe(struct platform_device *pdev)
194*4882a593Smuzhiyun {
195*4882a593Smuzhiyun struct device *dev = &pdev->dev;
196*4882a593Smuzhiyun struct clk_init_data init;
197*4882a593Smuzhiyun struct hi6220_stub_clk *stub_clk;
198*4882a593Smuzhiyun struct clk *clk;
199*4882a593Smuzhiyun struct device_node *np = pdev->dev.of_node;
200*4882a593Smuzhiyun int ret;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun stub_clk = devm_kzalloc(dev, sizeof(*stub_clk), GFP_KERNEL);
203*4882a593Smuzhiyun if (!stub_clk)
204*4882a593Smuzhiyun return -ENOMEM;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun stub_clk->dfs_map = syscon_regmap_lookup_by_phandle(np,
207*4882a593Smuzhiyun "hisilicon,hi6220-clk-sram");
208*4882a593Smuzhiyun if (IS_ERR(stub_clk->dfs_map)) {
209*4882a593Smuzhiyun dev_err(dev, "failed to get sram regmap\n");
210*4882a593Smuzhiyun return PTR_ERR(stub_clk->dfs_map);
211*4882a593Smuzhiyun }
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun stub_clk->hw.init = &init;
214*4882a593Smuzhiyun stub_clk->dev = dev;
215*4882a593Smuzhiyun stub_clk->id = HI6220_STUB_ACPU0;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun /* Use mailbox client with blocking mode */
218*4882a593Smuzhiyun stub_clk->cl.dev = dev;
219*4882a593Smuzhiyun stub_clk->cl.tx_done = NULL;
220*4882a593Smuzhiyun stub_clk->cl.tx_block = true;
221*4882a593Smuzhiyun stub_clk->cl.tx_tout = 500;
222*4882a593Smuzhiyun stub_clk->cl.knows_txdone = false;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun /* Allocate mailbox channel */
225*4882a593Smuzhiyun stub_clk->mbox = mbox_request_channel(&stub_clk->cl, 0);
226*4882a593Smuzhiyun if (IS_ERR(stub_clk->mbox)) {
227*4882a593Smuzhiyun dev_err(dev, "failed get mailbox channel\n");
228*4882a593Smuzhiyun return PTR_ERR(stub_clk->mbox);
229*4882a593Smuzhiyun }
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun init.name = "acpu0";
232*4882a593Smuzhiyun init.ops = &hi6220_stub_clk_ops;
233*4882a593Smuzhiyun init.num_parents = 0;
234*4882a593Smuzhiyun init.flags = 0;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun clk = devm_clk_register(dev, &stub_clk->hw);
237*4882a593Smuzhiyun if (IS_ERR(clk))
238*4882a593Smuzhiyun return PTR_ERR(clk);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
241*4882a593Smuzhiyun if (ret) {
242*4882a593Smuzhiyun dev_err(dev, "failed to register OF clock provider\n");
243*4882a593Smuzhiyun return ret;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* initialize buffer to zero */
247*4882a593Smuzhiyun regmap_write(stub_clk->dfs_map, ACPU_DFS_FLAG, 0x0);
248*4882a593Smuzhiyun regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_REQ, 0x0);
249*4882a593Smuzhiyun regmap_write(stub_clk->dfs_map, ACPU_DFS_FREQ_LMT, 0x0);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun dev_dbg(dev, "Registered clock '%s'\n", init.name);
252*4882a593Smuzhiyun return 0;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun static const struct of_device_id hi6220_stub_clk_of_match[] = {
256*4882a593Smuzhiyun { .compatible = "hisilicon,hi6220-stub-clk", },
257*4882a593Smuzhiyun {}
258*4882a593Smuzhiyun };
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun static struct platform_driver hi6220_stub_clk_driver = {
261*4882a593Smuzhiyun .driver = {
262*4882a593Smuzhiyun .name = "hi6220-stub-clk",
263*4882a593Smuzhiyun .of_match_table = hi6220_stub_clk_of_match,
264*4882a593Smuzhiyun },
265*4882a593Smuzhiyun .probe = hi6220_stub_clk_probe,
266*4882a593Smuzhiyun };
267*4882a593Smuzhiyun
hi6220_stub_clk_init(void)268*4882a593Smuzhiyun static int __init hi6220_stub_clk_init(void)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun return platform_driver_register(&hi6220_stub_clk_driver);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun subsys_initcall(hi6220_stub_clk_init);
273