Lines Matching +full:clock +full:- +full:freq
2 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/clock.h>
32 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
37 __raw_writel(reg, &imx_ccm->CCGR2); in enable_ocotp_clk()
45 clrbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
53 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
55 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
61 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); in setup_gpmi_io_clk()
63 clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_io_clk()
65 clrsetbits_le32(&imx_ccm->cs2cdr, in setup_gpmi_io_clk()
71 setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); in setup_gpmi_io_clk()
73 setbits_le32(&imx_ccm->CCGR4, in setup_gpmi_io_clk()
86 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
91 __raw_writel(reg, &imx_ccm->CCGR6); in enable_usboh3_clk()
102 addr = &imx_ccm->CCGR0; in enable_enet_clk()
105 addr = &imx_ccm->CCGR3; in enable_enet_clk()
108 addr = &imx_ccm->CCGR1; in enable_enet_clk()
129 setbits_le32(&imx_ccm->CCGR5, mask); in enable_uart_clk()
131 clrbits_le32(&imx_ccm->CCGR5, mask); in enable_uart_clk()
141 return -EINVAL; in enable_usdhc_clk()
145 setbits_le32(&imx_ccm->CCGR6, mask); in enable_usdhc_clk()
147 clrbits_le32(&imx_ccm->CCGR6, mask); in enable_usdhc_clk()
154 /* i2c_num can be from 0 - 3 */
162 return -EINVAL; in enable_i2c_clk()
167 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
172 __raw_writel(reg, &imx_ccm->CCGR2); in enable_i2c_clk()
175 return -EINVAL; in enable_i2c_clk()
178 addr = &imx_ccm->CCGR6; in enable_i2c_clk()
181 addr = &imx_ccm->CCGR1; in enable_i2c_clk()
194 /* spi_num can be from 0 - SPI_MAX_NUM */
201 return -EINVAL; in enable_spi_clk()
204 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
209 __raw_writel(reg, &imx_ccm->CCGR1); in enable_spi_clk()
218 div = __raw_readl(&imx_ccm->analog_pll_sys); in decode_pll()
223 div = __raw_readl(&imx_ccm->analog_pll_528); in decode_pll()
228 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); in decode_pll()
233 div = __raw_readl(&imx_ccm->analog_pll_enet); in decode_pll()
238 div = __raw_readl(&imx_ccm->analog_pll_audio); in decode_pll()
244 pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num); in decode_pll()
245 pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom); in decode_pll()
253 test_div = 1 << (2 - test_div); in decode_pll()
257 div = __raw_readl(&imx_ccm->analog_pll_video); in decode_pll()
263 pll_num = __raw_readl(&imx_ccm->analog_pll_video_num); in decode_pll()
264 pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom); in decode_pll()
272 test_div = 1 << (2 - test_div); in decode_pll()
283 u64 freq; in mxc_get_pll_pfd() local
293 div = __raw_readl(&imx_ccm->analog_pfd_528); in mxc_get_pll_pfd()
294 freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); in mxc_get_pll_pfd()
297 div = __raw_readl(&imx_ccm->analog_pfd_480); in mxc_get_pll_pfd()
298 freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); in mxc_get_pll_pfd()
305 return lldiv(freq * 18, (div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> in mxc_get_pll_pfd()
311 u32 reg, freq; in get_mcu_main_clk() local
313 reg = __raw_readl(&imx_ccm->cacrr); in get_mcu_main_clk()
316 freq = decode_pll(PLL_SYS, MXC_HCLK); in get_mcu_main_clk()
318 return freq / (reg + 1); in get_mcu_main_clk()
323 u32 reg, div = 0, freq = 0; in get_periph_clk() local
325 reg = __raw_readl(&imx_ccm->cbcdr); in get_periph_clk()
329 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
335 freq = decode_pll(PLL_USBOTG, MXC_HCLK); in get_periph_clk()
339 freq = MXC_HCLK; in get_periph_clk()
345 reg = __raw_readl(&imx_ccm->cbcmr); in get_periph_clk()
351 freq = decode_pll(PLL_BUS, MXC_HCLK); in get_periph_clk()
354 freq = mxc_get_pll_pfd(PLL_BUS, 2); in get_periph_clk()
357 freq = mxc_get_pll_pfd(PLL_BUS, 0); in get_periph_clk()
361 freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; in get_periph_clk()
368 return freq / (div + 1); in get_periph_clk()
375 reg = __raw_readl(&imx_ccm->cbcdr); in get_ipg_clk()
386 reg = __raw_readl(&imx_ccm->cscmr1); in get_ipg_per_clk()
401 u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ in get_uart_clk() local
402 reg = __raw_readl(&imx_ccm->cscdr1); in get_uart_clk()
407 freq = MXC_HCLK; in get_uart_clk()
413 return freq / (uart_podf + 1); in get_uart_clk()
420 reg = __raw_readl(&imx_ccm->cscdr2); in get_cspi_clk()
436 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_axi_clk()
456 cscmr1 = __raw_readl(&imx_ccm->cscmr1); in get_emi_slow_clk()
482 u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); in get_mmdc_ch0_clk()
483 u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); in get_mmdc_ch0_clk()
485 u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; in get_mmdc_ch0_clk() local
496 freq = MXC_HCLK; in get_mmdc_ch0_clk()
498 freq = decode_pll(PLL_USBOTG, MXC_HCLK); in get_mmdc_ch0_clk()
501 freq = decode_pll(PLL_BUS, MXC_HCLK); in get_mmdc_ch0_clk()
503 freq = decode_pll(PLL_USBOTG, MXC_HCLK); in get_mmdc_ch0_clk()
511 freq = decode_pll(PLL_BUS, MXC_HCLK); in get_mmdc_ch0_clk()
514 freq = mxc_get_pll_pfd(PLL_BUS, 2); in get_mmdc_ch0_clk()
517 freq = mxc_get_pll_pfd(PLL_BUS, 0); in get_mmdc_ch0_clk()
521 freq = mxc_get_pll_pfd(PLL_BUS, 2) >> 1; in get_mmdc_ch0_clk()
525 pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); in get_mmdc_ch0_clk()
538 freq = decode_pll(PLL_AUDIO, MXC_HCLK) / in get_mmdc_ch0_clk()
543 return freq / (podf + 1) / (per2_clk2_podf + 1); in get_mmdc_ch0_clk()
566 &imx_ccm->analog_pll_video_clr); in enable_pll_video()
573 &imx_ccm->analog_pll_video_set); in enable_pll_video()
578 &imx_ccm->analog_pll_video_set); in enable_pll_video()
583 &imx_ccm->analog_pll_video_set); in enable_pll_video()
587 return -EINVAL; in enable_pll_video()
591 &imx_ccm->analog_pll_video_num); in enable_pll_video()
593 &imx_ccm->analog_pll_video_denom); in enable_pll_video()
599 reg = readl(&imx_ccm->analog_pll_video); in enable_pll_video()
603 &imx_ccm->analog_pll_video_set); in enable_pll_video()
610 return -ETIME; in enable_pll_video()
614 * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
616 * 'freq' using KHz as unit, see driver/video/mxsfb.c.
618 void mxs_set_lcdclk(u32 base_addr, u32 freq) in mxs_set_lcdclk() argument
629 debug("mxs_set_lcdclk, freq = %dKHz\n", freq); in mxs_set_lcdclk()
639 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
640 /* Can't change clocks when clock not from pre-mux */ in mxs_set_lcdclk()
647 reg = readl(&imx_ccm->cscdr2); in mxs_set_lcdclk()
648 /* Can't change clocks when clock not from pre-mux */ in mxs_set_lcdclk()
653 temp = freq * max_pred * max_postd; in mxs_set_lcdclk()
666 freq *= post_div; in mxs_set_lcdclk()
672 printf("Fail to set rate to %dkhz", freq); in mxs_set_lcdclk()
677 /* Choose the best pred and postd to match freq for lcd */ in mxs_set_lcdclk()
680 temp = freq * i * j; in mxs_set_lcdclk()
692 printf("Fail to set rate to %dKHz", freq); in mxs_set_lcdclk()
700 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
704 * (24MHz * (pll_div + --------- )) in mxs_set_lcdclk()
706 *freq KHz = -------------------------------- in mxs_set_lcdclk()
716 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
717 clrsetbits_le32(&imx_ccm->cscdr2, in mxs_set_lcdclk()
721 ((pred - 1) << in mxs_set_lcdclk()
725 clrsetbits_le32(&imx_ccm->cbcmr, in mxs_set_lcdclk()
727 ((postd - 1) << in mxs_set_lcdclk()
730 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
731 clrsetbits_le32(&imx_ccm->cscdr2, in mxs_set_lcdclk()
735 ((pred - 1) << in mxs_set_lcdclk()
739 clrsetbits_le32(&imx_ccm->cscmr1, in mxs_set_lcdclk()
741 (((postd - 1)^0x6) << in mxs_set_lcdclk()
752 /* Select pre-lcd clock to PLL5 and set pre divider */ in mxs_set_lcdclk()
753 clrsetbits_le32(&imx_ccm->cscdr2, in mxs_set_lcdclk()
757 ((pred - 1) << in mxs_set_lcdclk()
761 clrsetbits_le32(&imx_ccm->cscmr1, in mxs_set_lcdclk()
763 ((postd - 1) << in mxs_set_lcdclk()
779 return -EINVAL; in enable_lcdif_clock()
781 /* Set to pre-mux clock at default */ in enable_lcdif_clock()
793 return -EINVAL; in enable_lcdif_clock()
795 /* Set to pre-mux clock at default */ in enable_lcdif_clock()
801 return -EINVAL; in enable_lcdif_clock()
804 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
807 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
810 reg = readl(&imx_ccm->cscdr3); in enable_lcdif_clock()
813 writel(reg, &imx_ccm->cscdr3); in enable_lcdif_clock()
815 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
818 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
826 /* Gate LCDIF clock first */ in enable_lcdif_clock()
827 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
829 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
831 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
833 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
836 /* Select pre-mux */ in enable_lcdif_clock()
837 reg = readl(&imx_ccm->cscdr2); in enable_lcdif_clock()
839 writel(reg, &imx_ccm->cscdr2); in enable_lcdif_clock()
841 /* Enable the LCDIF pix clock */ in enable_lcdif_clock()
842 reg = readl(&imx_ccm->CCGR3); in enable_lcdif_clock()
844 writel(reg, &imx_ccm->CCGR3); in enable_lcdif_clock()
846 reg = readl(&imx_ccm->CCGR2); in enable_lcdif_clock()
848 writel(reg, &imx_ccm->CCGR2); in enable_lcdif_clock()
856 /* qspi_num can be from 0 - 1 */
860 /* Enable QuadSPI clock */ in enable_qspi_clk()
863 /* disable the clock gate */ in enable_qspi_clk()
864 clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
867 reg = readl(&imx_ccm->cscmr1); in enable_qspi_clk()
872 writel(reg, &imx_ccm->cscmr1); in enable_qspi_clk()
874 /* enable the clock gate */ in enable_qspi_clk()
875 setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK); in enable_qspi_clk()
879 * disable the clock gate in enable_qspi_clk()
880 * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate, in enable_qspi_clk()
883 clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | in enable_qspi_clk()
887 reg = readl(&imx_ccm->cs2cdr); in enable_qspi_clk()
893 writel(reg, &imx_ccm->cs2cdr); in enable_qspi_clk()
895 /*enable the clock gate*/ in enable_qspi_clk()
896 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK | in enable_qspi_clk()
906 int enable_fec_anatop_clock(int fec_id, enum enet_freq freq) in enable_fec_anatop_clock() argument
914 if (freq < ENET_25MHZ || freq > ENET_125MHZ) in enable_fec_anatop_clock()
915 return -EINVAL; in enable_fec_anatop_clock()
917 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()
921 reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq); in enable_fec_anatop_clock()
925 return -EINVAL; in enable_fec_anatop_clock()
927 reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq); in enable_fec_anatop_clock()
929 return -EINVAL; in enable_fec_anatop_clock()
935 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
936 while (timeout--) { in enable_fec_anatop_clock()
937 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) in enable_fec_anatop_clock()
941 return -ETIMEDOUT; in enable_fec_anatop_clock()
944 /* Enable FEC clock */ in enable_fec_anatop_clock()
950 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
953 /* Disable enet system clcok before switching clock parent */ in enable_fec_anatop_clock()
954 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
956 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
959 * Set enet ahb clock to 200MHz in enable_fec_anatop_clock()
960 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB in enable_fec_anatop_clock()
962 reg = readl(&imx_ccm->chsccdr); in enable_fec_anatop_clock()
971 writel(reg, &imx_ccm->chsccdr); in enable_fec_anatop_clock()
973 /* Enable enet system clock */ in enable_fec_anatop_clock()
974 reg = readl(&imx_ccm->CCGR3); in enable_fec_anatop_clock()
976 writel(reg, &imx_ccm->CCGR3); in enable_fec_anatop_clock()
985 u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1); in get_usdhc_clk()
986 u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1); in get_usdhc_clk()
1054 reg = readl(&imx_ccm->analog_pll_enet); in enable_enet_pll()
1056 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1058 while (timeout--) { in enable_enet_pll()
1059 if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) in enable_enet_pll()
1063 return -EIO; in enable_enet_pll()
1065 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1067 writel(reg, &imx_ccm->analog_pll_enet); in enable_enet_pll()
1078 /* Enable SATA clock. */ in ungate_sata_clock()
1079 setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); in ungate_sata_clock()
1093 clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK); in disable_sata_clock()
1103 /* Enable PCIe clock. */ in ungate_pcie_clock()
1104 setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK); in ungate_pcie_clock()
1122 * Switch LVDS clock source to SATA (0xb) on mx6q/dl or PCI (0xa) on in enable_pcie_clock()
1123 * mx6sx, disable clock INPUT and enable clock OUTPUT. This is important in enable_pcie_clock()
1137 clrsetbits_le32(&anatop_regs->ana_misc1, in enable_pcie_clock()
1142 /* PCIe reference clock sourced from AXI. */ in enable_pcie_clock()
1143 clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); in enable_pcie_clock()
1145 /* Party time! Ungate the clock to the PCIe. */ in enable_pcie_clock()
1162 /* CG5, DCP clock */ in hab_caam_clock_enable()
1163 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1168 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1171 reg = __raw_readl(&imx_ccm->CCGR0); in hab_caam_clock_enable()
1180 __raw_writel(reg, &imx_ccm->CCGR0); in hab_caam_clock_enable()
1184 reg = __raw_readl(&imx_ccm->CCGR6); in hab_caam_clock_enable()
1189 __raw_writel(reg, &imx_ccm->CCGR6); in hab_caam_clock_enable()
1199 if ((readl(&anatop->usb1_pll_480_ctrl) & in enable_pll3()
1203 &anatop->usb1_pll_480_ctrl_set); in enable_pll3()
1204 writel(0x80, &anatop->ana_misc2_clr); in enable_pll3()
1206 while ((readl(&anatop->usb1_pll_480_ctrl) & in enable_pll3()
1211 &anatop->usb1_pll_480_ctrl_clr); in enable_pll3()
1214 &anatop->usb1_pll_480_ctrl_set); in enable_pll3()
1270 u32 freq; in do_mx6_showclocks() local
1271 freq = decode_pll(PLL_SYS, MXC_HCLK); in do_mx6_showclocks()
1272 printf("PLL_SYS %8d MHz\n", freq / 1000000); in do_mx6_showclocks()
1273 freq = decode_pll(PLL_BUS, MXC_HCLK); in do_mx6_showclocks()
1274 printf("PLL_BUS %8d MHz\n", freq / 1000000); in do_mx6_showclocks()
1275 freq = decode_pll(PLL_USBOTG, MXC_HCLK); in do_mx6_showclocks()
1276 printf("PLL_OTG %8d MHz\n", freq / 1000000); in do_mx6_showclocks()
1277 freq = decode_pll(PLL_ENET, MXC_HCLK); in do_mx6_showclocks()
1278 printf("PLL_NET %8d MHz\n", freq / 1000000); in do_mx6_showclocks()
1305 reg = readl(&mxc_ccm->CCGR3); in enable_ipu_clock()
1307 writel(reg, &mxc_ccm->CCGR3); in enable_ipu_clock()
1310 setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); in enable_ipu_clock()
1311 setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); in enable_ipu_clock()
1324 reg = readl(&mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1325 /* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */ in disable_ldb_di_clock_sources()
1330 writel(reg, &mxc_ccm->analog_pfd_528); in disable_ldb_di_clock_sources()
1333 reg = readl(&mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1335 writel(reg, &mxc_ccm->analog_pfd_480); in disable_ldb_di_clock_sources()
1338 reg = readl(&mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1340 writel(reg, &mxc_ccm->analog_pll_video); in disable_ldb_di_clock_sources()
1348 reg = readl(&mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1353 writel(reg, &mxc_ccm->analog_pfd_528); in enable_ldb_di_clock_sources()
1355 reg = readl(&mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1357 writel(reg, &mxc_ccm->analog_pfd_480); in enable_ldb_di_clock_sources()
1371 * clock, else we can introduce a glitch. Things to keep in in select_ldb_di_clock_source()
1374 * 2. The default clock for ldb_dio_clk is mmdc_ch1 which has in select_ldb_di_clock_source()
1384 * Need to disable MMDC_CH1 clock manually as there is no CG bit in select_ldb_di_clock_source()
1385 * for this clock. The only way to disable this clock is to move in select_ldb_di_clock_source()
1390 /* Disable all ldb_di clock parents */ in select_ldb_di_clock_source()
1394 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1396 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1399 reg = readl(&mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1401 writel(reg, &mxc_ccm->cbcmr); in select_ldb_di_clock_source()
1407 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1409 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1411 /* Wait for the clock switch */ in select_ldb_di_clock_source()
1412 while (readl(&mxc_ccm->cdhipr)) in select_ldb_di_clock_source()
1414 /* Disable pll3_sw_clk by selecting bypass clock source */ in select_ldb_di_clock_source()
1415 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1417 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1420 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1423 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1426 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1431 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1434 reg = readl(&mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1439 writel(reg, &mxc_ccm->cs2cdr); in select_ldb_di_clock_source()
1442 reg = readl(&mxc_ccm->ccsr); in select_ldb_di_clock_source()
1444 writel(reg, &mxc_ccm->ccsr); in select_ldb_di_clock_source()
1450 reg = readl(&mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1452 writel(reg, &mxc_ccm->cbcdr); in select_ldb_di_clock_source()
1454 /* Wait for the clock switch */ in select_ldb_di_clock_source()
1455 while (readl(&mxc_ccm->cdhipr)) in select_ldb_di_clock_source()
1458 reg = readl(&mxc_ccm->ccdr); in select_ldb_di_clock_source()
1460 writel(reg, &mxc_ccm->ccdr); in select_ldb_di_clock_source()
1471 reg = __raw_readl(&imx_ccm->CCGR6); in enable_eim_clk()
1476 __raw_writel(reg, &imx_ccm->CCGR6); in enable_eim_clk()