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/OK3568_Linux_fs/kernel/drivers/gpu/drm/hisilicon/kirin/kirin960/
H A Ddw_drm_dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2014-2016 Hisilicon Limited.
39 #define DTS_COMP_DSI_NAME "hisilicon,hi3660-dsi"
40 #define DSS_REDUCE(x) ((x) > 0 ? ((x) - 1) : (x))
61 u32 mask = (1UL << bw) - 1UL; in set_reg()
80 DRM_DEBUG_DRIVER("Checking mode %ix%i@%i clock: %i...", mode->hdisplay, in dsi_encoder_phy_mode_valid()
81 mode->vdisplay, drm_mode_vrefresh(mode), mode->clock); in dsi_encoder_phy_mode_valid()
82 if ((mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 148500) || in dsi_encoder_phy_mode_valid()
83 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 80192) || in dsi_encoder_phy_mode_valid()
84 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 74250) || in dsi_encoder_phy_mode_valid()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dfixed-clock.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
15 const: fixed-clock
17 "#clock-cells":
20 clock-frequency: true
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/OK3568_Linux_fs/kernel/drivers/clk/
H A Dclk-fixed-rate.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 * Fixed rate clock implementation
9 #include <linux/clk-provider.h>
18 * DOC: basic fixed-rate clock that cannot gate
20 * Traits of this clock:
21 * prepare - clk_(un)prepare only ensures parents are prepared
22 * enable - clk_enable only ensures parents are enabled
23 * rate - rate is always a fixed value. No clk_set_rate support
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H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
10 #include <linux/clk-provider.h>
11 #include <linux/clk/clk-conf.h>
82 unsigned long accuracy; member
115 if (!core->rpm_enabled) in clk_pm_runtime_get()
118 ret = pm_runtime_get_sync(core->dev); in clk_pm_runtime_get()
120 pm_runtime_put_noidle(core->dev); in clk_pm_runtime_get()
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynqmp-clk.dtsi2 * Clock specification for Xilinx ZynqMP
8 * SPDX-License-Identifier: GPL-2.0+
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <100000000>;
16 u-boot,dm-pre-reloc;
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <125000000>;
26 compatible = "fixed-clock";
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H A Dzynqmp-ep108-clk.dtsi2 * clock specification for Xilinx ZynqMP ep108 development board
8 * SPDX-License-Identifier: GPL-2.0+
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <25000000>;
16 u-boot,dm-pre-reloc;
20 compatible = "fixed-clock";
21 #clock-cells = <0x0>;
22 clock-frequency = <111111111>;
26 compatible = "fixed-clock";
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/OK3568_Linux_fs/kernel/Documentation/timers/
H A Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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/OK3568_Linux_fs/kernel/Documentation/hwmon/
H A Dpc87360.rst22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
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H A Dshtc1.rst41 -----------
48 address 0x70. See Documentation/i2c/instantiating-devices.rst for methods to
53 1. blocking (pull the I2C clock line down while performing the measurement) or
54 non-blocking mode. Blocking mode will guarantee the fastest result but
55 the I2C bus will be busy during that time. By default, non-blocking mode
56 is used. Make sure clock-stretching works properly on your device if you
58 2. high or low accuracy. High accuracy is used by default and using it is
61 sysfs-Interface
62 ---------------
65 - temperature input
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H A Dsht3x.rst6 * Sensirion SHT3x-DIS
16 - David Frey <david.frey@sensirion.com>
17 - Pascal Sachs <pascal.sachs@sensirion.com>
20 -----------
22 This driver implements support for the Sensirion SHT3x-DIS chip, a humidity
29 Documentation/i2c/instantiating-devices.rst for methods to instantiate the device.
33 1. blocking (pull the I2C clock line down while performing the measurement) or
34 non-blocking mode. Blocking mode will guarantee the fastest result but
35 the I2C bus will be busy during that time. By default, non-blocking mode
36 is used. Make sure clock-stretching works properly on your device if you
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/OK3568_Linux_fs/kernel/include/linux/
H A Dclk-provider.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14 * top-level framework. custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
31 /* parents need enable during gate/ungate, set rate and re-parent */
33 /* duty cycle call may be forwarded to the parent clock */
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/OK3568_Linux_fs/yocto/meta-openembedded/meta-networking/recipes-support/chrony/
H A Dchrony_4.2.bb2 DESCRIPTION = "Chrony can synchronize the system clock with NTP \
14 Typical accuracy between two machines on a LAN is in tens, or a few \
15 hundreds, of microseconds; over the Internet, accuracy is typically \
16 within a few milliseconds. With a good hardware reference clock \
17 sub-microsecond accuracy is possible. \
20 started at boot time and chronyc is a command-line interface program \
30 LICENSE = "GPL-2.0-only"
33 SRC_URI = "https://download.tuxfamily.org/chrony/chrony-${PV}.tar.gz \
39 SRC_URI:append:libc-musl = " \
40 file://0001-Fix-compilation-with-musl.patch \
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/OK3568_Linux_fs/u-boot/drivers/clk/at91/
H A DKconfig2 bool "AT91 clock drivers"
6 This option is used to enable the AT91 clock driver.
7 The driver supports the AT91 clock generator, including
8 the oscillators and PLLs, such as main clock, slow clock,
9 PLLA, UTMI PLL. Clocks can also be a source clock of other
10 clocks a tree structure, such as master clock, usb device
11 clock, matrix clock and generic clock.
12 Devices can use a common clock API to request a particular
13 clock, enable it and get its rate.
16 bool "Support UTMI PLL Clock"
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/OK3568_Linux_fs/kernel/Documentation/sound/designs/
H A Dtimestamping.rst7 - Trigger_tstamp is the system time snapshot taken when the .trigger
11 estimate with a delay. In the latter two cases, the low-level driver
17 - tstamp is the current system timestamp updated during the last
19 The difference (tstamp - trigger_tstamp) defines the elapsed time.
29 - ``avail`` reports how much can be written in the ring buffer
30 - ``delay`` reports the time it will take to hear a new sample after all
43 ascii-art, this could be represented as follows (for the playback
47 --------------------------------------------------------------> time
53 |< codec delay >|<--hw delay-->|<queued samples>|<---avail->|
54 |<----------------- delay---------------------->| |
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/OK3568_Linux_fs/kernel/drivers/clk/at91/
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
31 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
48 "atmel,sama5d2-clk-audio-pll-frac",
54 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
71 "atmel,sama5d2-clk-audio-pll-pad",
77 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
94 "atmel,sama5d2-clk-audio-pll-pmc",
148 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
149 name = gcknp->name; in of_sama5d2_clk_generated_setup()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dalphascale-asm9260.dtsi2 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
7 #include <dt-bindings/clock/alphascale,asm9260.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&icoll>;
20 #address-cells = <0>;
21 #size-cells = <0>;
24 compatible = "arm,arm926ej-s";
31 compatible = "fixed-clock";
32 #clock-cells = <0>;
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H A Dpxa300-raumfeld-tuneable-clock.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/maxim,max9485.h>
6 xo_27mhz: oscillator-27mhz {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <27000000>;
10 clock-accuracy = <100>;
14 compatible = "simple-audio-card";
15 simple-audio-card,name = "Raumfeld Speaker";
16 #address-cells = <1>;
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H A Dpxa300-raumfeld-speaker-one.dts1 // SPDX-License-Identifier: GPL-2.0
3 /dts-v1/;
5 #include "pxa300-raumfeld-common.dtsi"
9 compatible = "raumfeld,raumfeld-speaker-one-pxa303", "marvell,pxa300";
13 #sound-dai-cells = <0>;
14 Vdd-supply = <&reg_3v3>;
15 Vdda-supply = <&reg_va_5v0>;
18 xo_11mhz: oscillator-11mhz {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
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H A Dsun8i-v3s.dtsi4 * This file is dual-licensed: you can use it either under the terms
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
45 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
46 #include <dt-bindings/clock/sun8i-de2.h>
49 #address-cells = <1>;
50 #size-cells = <1>;
51 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/rtc/
H A DKconfig5 menu "Real Time Clock"
11 Enable drver model for real-time-clock drivers. The RTC uclass
20 The PCF2127 is a CMOS Real Time Clock (RTC) and calendar with an integrated
22 crystal optimized for very high accuracy and very low power consumption. The PCF2127
23 has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a
31 compatible Real Time Clock devices.
/OK3568_Linux_fs/kernel/arch/x86/kernel/
H A Dtsc_msr.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <asm/intel-family.h>
23 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
26 * unclear if the root PLL outputs are used directly by the CPU clock PLL or
30 * So we can create a simplified model of the CPU clock setup using a reference
31 * clock of 100 MHz plus a quotient which gets us as close to the frequency
62 * Penwell and Clovertrail use spread spectrum clock,
161 * MSR-based CPU/TSC frequency discovery for certain CPUs.
179 freq_desc = (struct freq_desc *)id->driver_data; in cpu_khz_from_msr()
180 if (freq_desc->use_msr_plat) { in cpu_khz_from_msr()
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/OK3568_Linux_fs/yocto/meta-openembedded/meta-networking/recipes-support/chrony/chrony/
H A Dchrony.conf11 # Sync to pulse-per-second from an onboard GPS.
16 # compatible = "pps-gpio";
20 # In first three updates step the system clock instead of slew
24 # Record the rate at which the system clock gains/loses time,
25 # improving accuracy after reboot
28 # Enable kernel synchronization of the hardware real-time clock (RTC).
/OK3568_Linux_fs/kernel/drivers/video/fbdev/kyro/
H A DSTG4000InitDevice.c41 /* Core clock freq */
44 /* Reference Clock freq */
61 /* PLL Clock */
101 /* Program SD-RAM interface */ in InitSDRAMRegisters()
129 /* Translate clock in Hz */ in ProgramClock()
133 /* Work out acceptable clock in ProgramClock()
134 * The method calculates ~ +- 0.4% (1/256) in ProgramClock()
136 ulMinClock = coreClock - (coreClock >> 8); in ProgramClock()
139 /* Scale clock required for use in calculations */ in ProgramClock()
147 /* loop for pre-divider from min to max */ in ProgramClock()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Drohm,bd70528-pmic.txt3 BD70528MWV is an ultra-low quiescent current general purpose, single-chip,
4 power management IC for battery-powered portable devices. The IC
5 integrates 3 ultra-low current consumption buck converters, 3 LDOs and 2
6 LED Drivers. Also included are 4 GPIOs, a real-time clock (RTC), a 32kHz
7 clock gate, high-accuracy VREF for use with an external ADC, flexible
8 dual-input power path, 10 bit SAR ADC for battery temperature monitor and
12 - compatible : Should be "rohm,bd70528"
13 - reg : I2C slave address.
14 - interrupts : The interrupt line the device is connected to.
15 - interrupt-controller : To indicate BD70528 acts as an interrupt controller.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Dti,adc12138.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments ADC12138 and similar self-calibrating ADCs
10 - Akinobu Mita <akinobu.mita@gmail.com>
19 - ti,adc12130
20 - ti,adc12132
21 - ti,adc12138
32 description: Conversion clock input.
34 spi-max-frequency: true
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