1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * DesignWare MIPI DSI Host Controller v1.02 driver
4 *
5 * Copyright (c) 2016 Linaro Limited.
6 * Copyright (c) 2014-2016 Hisilicon Limited.
7 *
8 * Author:
9 * <shizongxuan@huawei.com>
10 * <zhangxiubin@huawei.com>
11 * <lvda3@hisilicon.com>
12 *
13 */
14
15 #include <linux/clk.h>
16 #include <linux/module.h>
17 #include <linux/component.h>
18 #include <linux/of_graph.h>
19 #include <linux/iopoll.h>
20 #include <video/mipi_display.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/of_address.h>
23
24 #include <drm/drm_of.h>
25 #include <drm/drm_crtc_helper.h>
26 #include <drm/drm_mipi_dsi.h>
27 #include <drm/drm_encoder_slave.h>
28 #include <drm/drm_atomic_helper.h>
29 #include <drm/drm_panel.h>
30 #include <drm/drm_device.h>
31 #include <drm/drm_sysfs.h>
32 #include <drm/drm_print.h>
33 #include <drm/drm_probe_helper.h>
34
35 #include "../kirin_drm_dsi.h"
36 #include "../dw_dsi_reg.h"
37 #include "../kirin_dpe_reg.h"
38
39 #define DTS_COMP_DSI_NAME "hisilicon,hi3660-dsi"
40 #define DSS_REDUCE(x) ((x) > 0 ? ((x) - 1) : (x))
41
42 #define DEFAULT_MIPI_CLK_RATE (192 * 100000L)
43 #define DEFAULT_PCLK_DSI_RATE (120 * 1000000L)
44
45 struct dss_rect {
46 s32 x;
47 s32 y;
48 s32 w;
49 s32 h;
50 };
51
52 enum {
53 DSI_1_LANES = 0,
54 DSI_2_LANES,
55 DSI_3_LANES,
56 DSI_4_LANES,
57 };
58
set_reg(char __iomem * addr,uint32_t val,uint8_t bw,uint8_t bs)59 static void set_reg(char __iomem *addr, uint32_t val, uint8_t bw, uint8_t bs)
60 {
61 u32 mask = (1UL << bw) - 1UL;
62 u32 tmp = 0;
63
64 tmp = readl(addr);
65 tmp &= ~(mask << bs);
66
67 writel(tmp | ((val & mask) << bs), addr);
68 }
69
70 static enum drm_mode_status
dsi_encoder_phy_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)71 dsi_encoder_phy_mode_valid(struct drm_encoder *encoder,
72 const struct drm_display_mode *mode)
73 {
74 /* XXX HACK whitelist for now, to move it out of
75 * common adv7511 code. This should be replaced by
76 * something closer to dsi_encoder_phy_mode_valid()
77 * found in:
78 * drivers/gpu/drm/hisilicon/kirin/dw_drm_dsi.c
79 */
80 DRM_DEBUG_DRIVER("Checking mode %ix%i@%i clock: %i...", mode->hdisplay,
81 mode->vdisplay, drm_mode_vrefresh(mode), mode->clock);
82 if ((mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 148500) ||
83 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 80192) ||
84 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 74250) ||
85 (mode->hdisplay == 1920 && mode->vdisplay == 1080 && mode->clock == 61855) ||
86 (mode->hdisplay == 1680 && mode->vdisplay == 1050 && mode->clock == 147116) ||
87 (mode->hdisplay == 1680 && mode->vdisplay == 1050 && mode->clock == 146250) ||
88 (mode->hdisplay == 1680 && mode->vdisplay == 1050 && mode->clock == 144589) ||
89 (mode->hdisplay == 1600 && mode->vdisplay == 1200 && mode->clock == 160961) ||
90 (mode->hdisplay == 1600 && mode->vdisplay == 900 && mode->clock == 118963) ||
91 (mode->hdisplay == 1440 && mode->vdisplay == 900 && mode->clock == 126991) ||
92 (mode->hdisplay == 1280 && mode->vdisplay == 1024 && mode->clock == 128946) ||
93 (mode->hdisplay == 1280 && mode->vdisplay == 1024 && mode->clock == 98619) ||
94 (mode->hdisplay == 1280 && mode->vdisplay == 960 && mode->clock == 102081) ||
95 (mode->hdisplay == 1280 && mode->vdisplay == 800 && mode->clock == 83496) ||
96 (mode->hdisplay == 1280 && mode->vdisplay == 720 && mode->clock == 74440) ||
97 (mode->hdisplay == 1280 && mode->vdisplay == 720 && mode->clock == 74250) ||
98 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 78800) ||
99 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 75000) ||
100 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 81833) ||
101 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 48907) ||
102 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||
103 (mode->hdisplay == 800 && mode->vdisplay == 480 && mode->clock == 32000)) {
104 DRM_DEBUG("OK\n");
105 return MODE_OK;
106 }
107 DRM_DEBUG("BAD\n");
108 return MODE_BAD;
109 }
110
111 static enum drm_mode_status
dsi_encoder_mode_valid(struct drm_encoder * encoder,const struct drm_display_mode * mode)112 dsi_encoder_mode_valid(struct drm_encoder *encoder,
113 const struct drm_display_mode *mode)
114
115 {
116 struct drm_crtc *crtc = NULL;
117 struct drm_display_mode adj_mode;
118 enum drm_mode_status ret;
119
120 /*
121 * The crtc might adjust the mode, so go through the
122 * possible crtcs (technically just one) and call
123 * mode_fixup to figure out the adjusted mode before we
124 * validate it.
125 */
126 drm_for_each_crtc(crtc, encoder->dev) {
127 /*
128 * reset adj_mode to the mode value each time,
129 * so we don't adjust the mode twice
130 */
131 drm_mode_copy(&adj_mode, mode);
132
133 #if 0
134 /* XXX - skip this as we're just using a whitelist */
135 crtc_funcs = crtc->helper_private;
136 if (crtc_funcs && crtc_funcs->mode_fixup)
137 if (!crtc_funcs->mode_fixup(crtc, mode, &adj_mode))
138 return MODE_BAD;
139 #endif
140 ret = dsi_encoder_phy_mode_valid(encoder, &adj_mode);
141 if (ret != MODE_OK)
142 return ret;
143 }
144 return MODE_OK;
145 }
146
get_dsi_phy_ctrl(struct dw_dsi * dsi,struct mipi_phy_params * phy_ctrl)147 static void get_dsi_phy_ctrl(struct dw_dsi *dsi,
148 struct mipi_phy_params *phy_ctrl)
149 {
150 struct mipi_panel_info *mipi = NULL;
151 struct drm_display_mode *mode = NULL;
152 u32 dphy_req_kHz;
153 int bpp;
154 u32 id = 0;
155 u32 ui = 0;
156 u32 m_pll = 0;
157 u32 n_pll = 0;
158 u32 m_n_fract = 0;
159 u32 m_n_int = 0;
160 u64 lane_clock = 0;
161 u64 vco_div = 1;
162
163 u32 accuracy = 0;
164 u32 unit_tx_byte_clk_hs = 0;
165 u32 clk_post = 0;
166 u32 clk_pre = 0;
167 u32 clk_t_hs_exit = 0;
168 u32 clk_pre_delay = 0;
169 u32 clk_t_hs_prepare = 0;
170 u32 clk_t_lpx = 0;
171 u32 clk_t_hs_zero = 0;
172 u32 clk_t_hs_trial = 0;
173 u32 data_post_delay = 0;
174 u32 data_t_hs_prepare = 0;
175 u32 data_t_hs_zero = 0;
176 u32 data_t_hs_trial = 0;
177 u32 data_t_lpx = 0;
178 u32 clk_pre_delay_reality = 0;
179 u32 clk_t_hs_zero_reality = 0;
180 u32 clk_post_delay_reality = 0;
181 u32 data_t_hs_zero_reality = 0;
182 u32 data_post_delay_reality = 0;
183 u32 data_pre_delay_reality = 0;
184
185 WARN_ON(!phy_ctrl);
186 WARN_ON(!dsi);
187
188 id = dsi->cur_client;
189 mode = &dsi->cur_mode;
190 mipi = &dsi->mipi;
191
192 /*
193 * count phy params
194 */
195 bpp = mipi_dsi_pixel_format_to_bpp(dsi->client[id].format);
196 if (bpp < 0)
197 return;
198 if (mode->clock > 80000)
199 dsi->client[id].lanes = 4;
200 else
201 dsi->client[id].lanes = 3;
202 if (dsi->client[id].phy_clock)
203 dphy_req_kHz = dsi->client[id].phy_clock;
204 else
205 dphy_req_kHz = mode->clock * bpp / dsi->client[id].lanes;
206
207 lane_clock = dphy_req_kHz / 1000;
208 DRM_DEBUG("Expected : lane_clock = %llu M\n", lane_clock);
209
210 /************************ PLL parameters config *********************/
211 /*
212 * chip spec :
213 * If the output data rate is below 320 Mbps,
214 * RG_BNAD_SEL should be set to 1.
215 * At this mode a post divider of 1/4 will be applied to VCO.
216 */
217 if (lane_clock >= 320 && lane_clock <= 2500) {
218 phy_ctrl->rg_band_sel = 0; /*0x1E[2]*/
219 vco_div = 1;
220 } else if (lane_clock >= 80 && lane_clock < 320) {
221 phy_ctrl->rg_band_sel = 1;
222 vco_div = 4;
223 } else {
224 DRM_ERROR("80M <= lane_clock< = 2500M, not support lane_clock = %llu M\n",
225 lane_clock);
226 }
227
228 m_n_int = lane_clock * vco_div * 1000000UL / DEFAULT_MIPI_CLK_RATE;
229 m_n_fract = ((lane_clock * vco_div * 1000000UL * 1000UL /
230 DEFAULT_MIPI_CLK_RATE) %
231 1000) *
232 10 / 1000;
233
234 if (m_n_int % 2 == 0) {
235 if (m_n_fract * 6 >= 50) {
236 n_pll = 2;
237 m_pll = (m_n_int + 1) * n_pll;
238 } else if (m_n_fract * 6 >= 30) {
239 n_pll = 3;
240 m_pll = m_n_int * n_pll + 2;
241 } else {
242 n_pll = 1;
243 m_pll = m_n_int * n_pll;
244 }
245 } else {
246 if (m_n_fract * 6 >= 50) {
247 n_pll = 1;
248 m_pll = (m_n_int + 1) * n_pll;
249 } else if (m_n_fract * 6 >= 30) {
250 n_pll = 1;
251 m_pll = (m_n_int + 1) * n_pll;
252 } else if (m_n_fract * 6 >= 10) {
253 n_pll = 3;
254 m_pll = m_n_int * n_pll + 1;
255 } else {
256 n_pll = 2;
257 m_pll = m_n_int * n_pll;
258 }
259 }
260
261 /*if set rg_pll_enswc=1, pll_fbd_s can't be 0*/
262 if (m_pll <= 8) {
263 phy_ctrl->pll_fbd_s = 1;
264 phy_ctrl->rg_pll_enswc = 0;
265
266 if (m_pll % 2 == 0) {
267 phy_ctrl->pll_fbd_p = m_pll / 2;
268 } else {
269 if (n_pll == 1) {
270 n_pll *= 2;
271 phy_ctrl->pll_fbd_p = (m_pll * 2) / 2;
272 } else {
273 DRM_ERROR("phy m_pll not support!m_pll = %d\n",
274 m_pll);
275 return;
276 }
277 }
278 } else if (m_pll <= 300) {
279 if (m_pll % 2 == 0)
280 phy_ctrl->rg_pll_enswc = 0;
281 else
282 phy_ctrl->rg_pll_enswc = 1;
283
284 phy_ctrl->pll_fbd_s = 1;
285 phy_ctrl->pll_fbd_p = m_pll / 2;
286 } else if (m_pll <= 315) {
287 phy_ctrl->pll_fbd_p = 150;
288 phy_ctrl->pll_fbd_s = m_pll - 2 * phy_ctrl->pll_fbd_p;
289 phy_ctrl->rg_pll_enswc = 1;
290 } else {
291 DRM_ERROR("phy m_pll not support!m_pll = %d\n", m_pll);
292 return;
293 }
294
295 phy_ctrl->pll_pre_p = n_pll;
296
297 lane_clock = m_pll * (DEFAULT_MIPI_CLK_RATE / n_pll) / vco_div;
298 DRM_DEBUG("Config : lane_clock = %llu\n", lane_clock);
299
300 /*FIXME :*/
301 phy_ctrl->rg_pll_cp = 1; /*0x16[7:5]*/
302 phy_ctrl->rg_pll_cp_p = 3; /*0x1E[7:5]*/
303
304 /*test_code_0x14 other parameters config*/
305 phy_ctrl->pll_enbwt = 0; /*0x14[2]*/
306 phy_ctrl->rg_pll_chp = 0; /*0x14[1:0]*/
307
308 /*test_code_0x16 other parameters config, 0x16[3:2] reserved*/
309 phy_ctrl->pll_lpf_cs = 0; /*0x16[4]*/
310 phy_ctrl->rg_pll_refsel = 1; /*0x16[1:0]*/
311
312 /*test_code_0x1E other parameters config*/
313 phy_ctrl->reload_sel = 1; /*0x1E[4]*/
314 phy_ctrl->rg_phase_gen_en = 1; /*0x1E[3]*/
315 phy_ctrl->pll_power_down = 0; /*0x1E[1]*/
316 phy_ctrl->pll_register_override = 1; /*0x1E[0]*/
317
318 /*HSTX select VCM VREF*/
319 phy_ctrl->rg_vrefsel_vcm = 0x55;
320 if (mipi->rg_vrefsel_vcm_clk_adjust != 0)
321 phy_ctrl->rg_vrefsel_vcm = (phy_ctrl->rg_vrefsel_vcm & 0x0F) |
322 ((mipi->rg_vrefsel_vcm_clk_adjust & 0x0F) << 4);
323
324 if (mipi->rg_vrefsel_vcm_data_adjust != 0)
325 phy_ctrl->rg_vrefsel_vcm = (phy_ctrl->rg_vrefsel_vcm & 0xF0) |
326 (mipi->rg_vrefsel_vcm_data_adjust & 0x0F);
327
328 /*if reload_sel = 1, need to set load_command*/
329 phy_ctrl->load_command = 0x5A;
330
331 /******************** clock/data lane parameters config ******************/
332 accuracy = 10;
333 ui = 10 * 1000000000UL * accuracy / lane_clock;
334 /*unit of measurement*/
335 unit_tx_byte_clk_hs = 8 * ui;
336
337 /* D-PHY Specification : 60ns + 52*UI <= clk_post*/
338 clk_post = 600 * accuracy + 52 * ui + mipi->clk_post_adjust * ui;
339
340 /* D-PHY Specification : clk_pre >= 8*UI*/
341 clk_pre = 8 * ui + mipi->clk_pre_adjust * ui;
342
343 /* D-PHY Specification : clk_t_hs_exit >= 100ns*/
344 clk_t_hs_exit = 1000 * accuracy + mipi->clk_t_hs_exit_adjust * ui;
345
346 /* clocked by TXBYTECLKHS*/
347 clk_pre_delay = 0 + mipi->clk_pre_delay_adjust * ui;
348
349 /* D-PHY Specification : clk_t_hs_trial >= 60ns*/
350 /* clocked by TXBYTECLKHS*/
351 clk_t_hs_trial = 600 * accuracy + 3 * unit_tx_byte_clk_hs +
352 mipi->clk_t_hs_trial_adjust * ui;
353
354 /* D-PHY Specification : 38ns <= clk_t_hs_prepare <= 95ns*/
355 /* clocked by TXBYTECLKHS*/
356 if (mipi->clk_t_hs_prepare_adjust == 0)
357 mipi->clk_t_hs_prepare_adjust = 43;
358
359 clk_t_hs_prepare =
360 ((380 * accuracy + mipi->clk_t_hs_prepare_adjust * ui) <=
361 (950 * accuracy - 8 * ui)) ?
362 (380 * accuracy + mipi->clk_t_hs_prepare_adjust * ui) :
363 (950 * accuracy - 8 * ui);
364
365 /* clocked by TXBYTECLKHS*/
366 data_post_delay = 0 + mipi->data_post_delay_adjust * ui;
367
368 /* D-PHY Specification : data_t_hs_trial >= max( n*8*UI, 60ns + n*4*UI ), n = 1*/
369 /* clocked by TXBYTECLKHS*/
370 data_t_hs_trial = ((600 * accuracy + 4 * ui) >= (8 * ui) ?
371 (600 * accuracy + 4 * ui) :
372 (8 * ui)) +
373 8 * ui + 3 * unit_tx_byte_clk_hs +
374 mipi->data_t_hs_trial_adjust * ui;
375
376 /* D-PHY Specification : 40ns + 4*UI <= data_t_hs_prepare <= 85ns + 6*UI*/
377 /* clocked by TXBYTECLKHS*/
378 if (mipi->data_t_hs_prepare_adjust == 0)
379 mipi->data_t_hs_prepare_adjust = 35;
380
381 data_t_hs_prepare = ((400 * accuracy + 4 * ui +
382 mipi->data_t_hs_prepare_adjust * ui) <=
383 (850 * accuracy + 6 * ui - 8 * ui)) ?
384 (400 * accuracy + 4 * ui +
385 mipi->data_t_hs_prepare_adjust * ui) :
386 (850 * accuracy + 6 * ui - 8 * ui);
387
388 /* D-PHY chip spec : clk_t_lpx + clk_t_hs_prepare > 200ns*/
389 /* D-PHY Specification : clk_t_lpx >= 50ns*/
390 /* clocked by TXBYTECLKHS*/
391 clk_t_lpx = (((2000 * accuracy - clk_t_hs_prepare) >= 500 * accuracy) ?
392 ((2000 * accuracy - clk_t_hs_prepare)) :
393 (500 * accuracy)) +
394 mipi->clk_t_lpx_adjust * ui;
395
396 /* D-PHY Specification : clk_t_hs_zero + clk_t_hs_prepare >= 300 ns*/
397 /* clocked by TXBYTECLKHS*/
398 clk_t_hs_zero = 3000 * accuracy - clk_t_hs_prepare +
399 3 * unit_tx_byte_clk_hs +
400 mipi->clk_t_hs_zero_adjust * ui;
401
402 /* D-PHY chip spec : data_t_lpx + data_t_hs_prepare > 200ns*/
403 /* D-PHY Specification : data_t_lpx >= 50ns*/
404 /* clocked by TXBYTECLKHS*/
405 data_t_lpx =
406 clk_t_lpx + mipi->data_t_lpx_adjust *
407 ui; /*2000 * accuracy - data_t_hs_prepare;*/
408
409 /* D-PHY Specification : data_t_hs_zero + data_t_hs_prepare >= 145ns + 10*UI*/
410 /* clocked by TXBYTECLKHS*/
411 data_t_hs_zero = 1450 * accuracy + 10 * ui - data_t_hs_prepare +
412 3 * unit_tx_byte_clk_hs +
413 mipi->data_t_hs_zero_adjust * ui;
414
415 phy_ctrl->clk_pre_delay = DIV_ROUND_UP(clk_pre_delay, unit_tx_byte_clk_hs);
416 phy_ctrl->clk_t_hs_prepare =
417 DIV_ROUND_UP(clk_t_hs_prepare, unit_tx_byte_clk_hs);
418 phy_ctrl->clk_t_lpx = DIV_ROUND_UP(clk_t_lpx, unit_tx_byte_clk_hs);
419 phy_ctrl->clk_t_hs_zero = DIV_ROUND_UP(clk_t_hs_zero, unit_tx_byte_clk_hs);
420 phy_ctrl->clk_t_hs_trial = DIV_ROUND_UP(clk_t_hs_trial, unit_tx_byte_clk_hs);
421
422 phy_ctrl->data_post_delay =
423 DIV_ROUND_UP(data_post_delay, unit_tx_byte_clk_hs);
424 phy_ctrl->data_t_hs_prepare =
425 DIV_ROUND_UP(data_t_hs_prepare, unit_tx_byte_clk_hs);
426 phy_ctrl->data_t_lpx = DIV_ROUND_UP(data_t_lpx, unit_tx_byte_clk_hs);
427 phy_ctrl->data_t_hs_zero = DIV_ROUND_UP(data_t_hs_zero, unit_tx_byte_clk_hs);
428 phy_ctrl->data_t_hs_trial =
429 DIV_ROUND_UP(data_t_hs_trial, unit_tx_byte_clk_hs);
430 phy_ctrl->data_t_ta_go = 4;
431 phy_ctrl->data_t_ta_get = 5;
432
433 clk_pre_delay_reality = phy_ctrl->clk_pre_delay + 2;
434 clk_t_hs_zero_reality = phy_ctrl->clk_t_hs_zero + 8;
435 data_t_hs_zero_reality = phy_ctrl->data_t_hs_zero + 4;
436 data_post_delay_reality = phy_ctrl->data_post_delay + 4;
437
438 phy_ctrl->clk_post_delay = phy_ctrl->data_t_hs_trial +
439 DIV_ROUND_UP(clk_post, unit_tx_byte_clk_hs);
440 phy_ctrl->data_pre_delay = clk_pre_delay_reality + phy_ctrl->clk_t_lpx +
441 phy_ctrl->clk_t_hs_prepare +
442 clk_t_hs_zero_reality +
443 DIV_ROUND_UP(clk_pre, unit_tx_byte_clk_hs);
444
445 clk_post_delay_reality = phy_ctrl->clk_post_delay + 4;
446 data_pre_delay_reality = phy_ctrl->data_pre_delay + 2;
447
448 phy_ctrl->clk_lane_lp2hs_time =
449 clk_pre_delay_reality + phy_ctrl->clk_t_lpx +
450 phy_ctrl->clk_t_hs_prepare + clk_t_hs_zero_reality + 3;
451 phy_ctrl->clk_lane_hs2lp_time =
452 clk_post_delay_reality + phy_ctrl->clk_t_hs_trial + 3;
453 phy_ctrl->data_lane_lp2hs_time =
454 data_pre_delay_reality + phy_ctrl->data_t_lpx +
455 phy_ctrl->data_t_hs_prepare + data_t_hs_zero_reality + 3;
456 phy_ctrl->data_lane_hs2lp_time =
457 data_post_delay_reality + phy_ctrl->data_t_hs_trial + 3;
458 phy_ctrl->phy_stop_wait_time =
459 clk_post_delay_reality + phy_ctrl->clk_t_hs_trial +
460 DIV_ROUND_UP(clk_t_hs_exit, unit_tx_byte_clk_hs) -
461 (data_post_delay_reality + phy_ctrl->data_t_hs_trial) + 3;
462
463 phy_ctrl->lane_byte_clk = lane_clock / 8;
464 phy_ctrl->clk_division =
465 (((phy_ctrl->lane_byte_clk / 2) % mipi->max_tx_esc_clk) > 0) ?
466 (phy_ctrl->lane_byte_clk / 2 / mipi->max_tx_esc_clk +
467 1) :
468 (phy_ctrl->lane_byte_clk / 2 / mipi->max_tx_esc_clk);
469
470 DRM_DEBUG("PHY clock_lane and data_lane config :\n"
471 "rg_vrefsel_vcm=%u\n"
472 "clk_pre_delay=%u\n"
473 "clk_post_delay=%u\n"
474 "clk_t_hs_prepare=%u\n"
475 "clk_t_lpx=%u\n"
476 "clk_t_hs_zero=%u\n"
477 "clk_t_hs_trial=%u\n"
478 "data_pre_delay=%u\n"
479 "data_post_delay=%u\n"
480 "data_t_hs_prepare=%u\n"
481 "data_t_lpx=%u\n"
482 "data_t_hs_zero=%u\n"
483 "data_t_hs_trial=%u\n"
484 "data_t_ta_go=%u\n"
485 "data_t_ta_get=%u\n",
486 phy_ctrl->rg_vrefsel_vcm, phy_ctrl->clk_pre_delay,
487 phy_ctrl->clk_post_delay, phy_ctrl->clk_t_hs_prepare,
488 phy_ctrl->clk_t_lpx, phy_ctrl->clk_t_hs_zero,
489 phy_ctrl->clk_t_hs_trial, phy_ctrl->data_pre_delay,
490 phy_ctrl->data_post_delay, phy_ctrl->data_t_hs_prepare,
491 phy_ctrl->data_t_lpx, phy_ctrl->data_t_hs_zero,
492 phy_ctrl->data_t_hs_trial, phy_ctrl->data_t_ta_go,
493 phy_ctrl->data_t_ta_get);
494 DRM_DEBUG("clk_lane_lp2hs_time=%u\n"
495 "clk_lane_hs2lp_time=%u\n"
496 "data_lane_lp2hs_time=%u\n"
497 "data_lane_hs2lp_time=%u\n"
498 "phy_stop_wait_time=%u\n",
499 phy_ctrl->clk_lane_lp2hs_time, phy_ctrl->clk_lane_hs2lp_time,
500 phy_ctrl->data_lane_lp2hs_time, phy_ctrl->data_lane_hs2lp_time,
501 phy_ctrl->phy_stop_wait_time);
502 }
503
dsi_set_burst_mode(void __iomem * base,unsigned long flags)504 static void dsi_set_burst_mode(void __iomem *base, unsigned long flags)
505 {
506 u32 val;
507 u32 mode_mask = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
508 MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
509 u32 non_burst_sync_pulse =
510 MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
511 u32 non_burst_sync_event = MIPI_DSI_MODE_VIDEO;
512
513 /*
514 * choose video mode type
515 */
516 if ((flags & mode_mask) == non_burst_sync_pulse)
517 val = DSI_NON_BURST_SYNC_PULSES;
518 else if ((flags & mode_mask) == non_burst_sync_event)
519 val = DSI_NON_BURST_SYNC_EVENTS;
520 else
521 val = DSI_BURST_SYNC_PULSES_1;
522
523 set_reg(base + MIPIDSI_VID_MODE_CFG_OFFSET, val, 2, 0);
524 }
525
526 /*
527 * dsi phy reg write function
528 */
dsi_phy_tst_set(void __iomem * base,u32 reg,u32 val)529 static void dsi_phy_tst_set(void __iomem *base, u32 reg, u32 val)
530 {
531 u32 reg_write = 0x10000 + reg;
532
533 /*
534 * latch reg first
535 */
536 writel(reg_write, base + MIPIDSI_PHY_TST_CTRL1_OFFSET);
537 writel(0x02, base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
538 writel(0x00, base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
539
540 /*
541 * then latch value
542 */
543 writel(val, base + MIPIDSI_PHY_TST_CTRL1_OFFSET);
544 writel(0x02, base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
545 writel(0x00, base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
546 }
547
dsi_mipi_init(struct dw_dsi * dsi,char __iomem * mipi_dsi_base)548 static void dsi_mipi_init(struct dw_dsi *dsi, char __iomem *mipi_dsi_base)
549 {
550 u32 hline_time = 0;
551 u32 hsa_time = 0;
552 u32 hbp_time = 0;
553 u64 pixel_clk = 0;
554 u32 i = 0;
555 u32 id = 0;
556 unsigned long dw_jiffies = 0;
557 u32 tmp = 0;
558 bool is_ready = false;
559 struct mipi_panel_info *mipi = NULL;
560 struct dss_rect rect;
561 u32 cmp_stopstate_val = 0;
562 u32 lanes;
563
564 WARN_ON(!dsi);
565 WARN_ON(!mipi_dsi_base);
566
567 id = dsi->cur_client;
568 mipi = &dsi->mipi;
569
570 if (mipi->max_tx_esc_clk == 0) {
571 DRM_ERROR("max_tx_esc_clk is invalid!");
572 mipi->max_tx_esc_clk = DEFAULT_MAX_TX_ESC_CLK;
573 }
574
575 memset(&dsi->phy, 0, sizeof(struct mipi_phy_params));
576 get_dsi_phy_ctrl(dsi, &dsi->phy);
577
578 rect.x = 0;
579 rect.y = 0;
580 rect.w = dsi->cur_mode.hdisplay;
581 rect.h = dsi->cur_mode.vdisplay;
582 lanes = dsi->client[id].lanes - 1;
583 /***************Configure the DPHY start**************/
584
585 set_reg(mipi_dsi_base + MIPIDSI_PHY_IF_CFG_OFFSET, lanes, 2, 0);
586 set_reg(mipi_dsi_base + MIPIDSI_CLKMGR_CFG_OFFSET,
587 dsi->phy.clk_division, 8, 0);
588 set_reg(mipi_dsi_base + MIPIDSI_CLKMGR_CFG_OFFSET,
589 dsi->phy.clk_division, 8, 8);
590
591 writel(0x00000000, mipi_dsi_base + MIPIDSI_PHY_RSTZ_OFFSET);
592
593 writel(0x00000000, mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
594 writel(0x00000001, mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
595 writel(0x00000000, mipi_dsi_base + MIPIDSI_PHY_TST_CTRL0_OFFSET);
596
597 /* physical configuration PLL I*/
598 dsi_phy_tst_set(mipi_dsi_base, 0x14, (dsi->phy.pll_fbd_s << 4) +
599 (dsi->phy.rg_pll_enswc << 3) +
600 (dsi->phy.pll_enbwt << 2) +
601 dsi->phy.rg_pll_chp);
602
603 /* physical configuration PLL II, M*/
604 dsi_phy_tst_set(mipi_dsi_base, 0x15, dsi->phy.pll_fbd_p);
605
606 /* physical configuration PLL III*/
607 dsi_phy_tst_set(mipi_dsi_base, 0x16, (dsi->phy.rg_pll_cp << 5) +
608 (dsi->phy.pll_lpf_cs << 4) +
609 dsi->phy.rg_pll_refsel);
610
611 /* physical configuration PLL IV, N*/
612 dsi_phy_tst_set(mipi_dsi_base, 0x17, dsi->phy.pll_pre_p);
613
614 /* sets the analog characteristic of V reference in D-PHY TX*/
615 dsi_phy_tst_set(mipi_dsi_base, 0x1D, dsi->phy.rg_vrefsel_vcm);
616
617 /* MISC AFE Configuration*/
618 dsi_phy_tst_set(mipi_dsi_base, 0x1E, (dsi->phy.rg_pll_cp_p << 5) +
619 (dsi->phy.reload_sel << 4) +
620 (dsi->phy.rg_phase_gen_en << 3) +
621 (dsi->phy.rg_band_sel << 2) +
622 (dsi->phy.pll_power_down << 1) +
623 dsi->phy.pll_register_override);
624
625 /*reload_command*/
626 dsi_phy_tst_set(mipi_dsi_base, 0x1F, dsi->phy.load_command);
627
628 /* pre_delay of clock lane request setting*/
629 dsi_phy_tst_set(mipi_dsi_base, 0x20,
630 DSS_REDUCE(dsi->phy.clk_pre_delay));
631
632 /* post_delay of clock lane request setting*/
633 dsi_phy_tst_set(mipi_dsi_base, 0x21,
634 DSS_REDUCE(dsi->phy.clk_post_delay));
635
636 /* clock lane timing ctrl - t_lpx*/
637 dsi_phy_tst_set(mipi_dsi_base, 0x22, DSS_REDUCE(dsi->phy.clk_t_lpx));
638
639 /* clock lane timing ctrl - t_hs_prepare*/
640 dsi_phy_tst_set(mipi_dsi_base, 0x23,
641 DSS_REDUCE(dsi->phy.clk_t_hs_prepare));
642
643 /* clock lane timing ctrl - t_hs_zero*/
644 dsi_phy_tst_set(mipi_dsi_base, 0x24,
645 DSS_REDUCE(dsi->phy.clk_t_hs_zero));
646
647 /* clock lane timing ctrl - t_hs_trial*/
648 dsi_phy_tst_set(mipi_dsi_base, 0x25, dsi->phy.clk_t_hs_trial);
649
650 for (i = 0; i <= lanes; i++) {
651 /* data lane pre_delay*/
652 tmp = 0x30 + (i << 4);
653 dsi_phy_tst_set(mipi_dsi_base, tmp,
654 DSS_REDUCE(dsi->phy.data_pre_delay));
655
656 /*data lane post_delay*/
657 tmp = 0x31 + (i << 4);
658 dsi_phy_tst_set(mipi_dsi_base, tmp,
659 DSS_REDUCE(dsi->phy.data_post_delay));
660
661 /* data lane timing ctrl - t_lpx*/
662 dsi_phy_tst_set(mipi_dsi_base, tmp,
663 DSS_REDUCE(dsi->phy.data_t_lpx));
664
665 /* data lane timing ctrl - t_hs_prepare*/
666 tmp = 0x33 + (i << 4);
667 dsi_phy_tst_set(mipi_dsi_base, tmp,
668 DSS_REDUCE(dsi->phy.data_t_hs_prepare));
669
670 /* data lane timing ctrl - t_hs_zero*/
671 tmp = 0x34 + (i << 4);
672 dsi_phy_tst_set(mipi_dsi_base, tmp,
673 DSS_REDUCE(dsi->phy.data_t_hs_zero));
674
675 /* data lane timing ctrl - t_hs_trial*/
676 tmp = 0x35 + (i << 4);
677 dsi_phy_tst_set(mipi_dsi_base, tmp,
678 DSS_REDUCE(dsi->phy.data_t_hs_trial));
679
680 /* data lane timing ctrl - t_ta_go*/
681 tmp = 0x36 + (i << 4);
682 dsi_phy_tst_set(mipi_dsi_base, tmp,
683 DSS_REDUCE(dsi->phy.data_t_ta_go));
684
685 /* data lane timing ctrl - t_ta_get*/
686 tmp = 0x37 + (i << 4);
687 dsi_phy_tst_set(mipi_dsi_base, tmp,
688 DSS_REDUCE(dsi->phy.data_t_ta_get));
689 }
690
691 writel(0x00000007, mipi_dsi_base + MIPIDSI_PHY_RSTZ_OFFSET);
692
693 is_ready = false;
694 dw_jiffies = jiffies + HZ / 2;
695 do {
696 tmp = readl(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
697 if ((tmp & 0x00000001) == 0x00000001) {
698 is_ready = true;
699 break;
700 }
701 } while (time_after(dw_jiffies, jiffies));
702
703 if (!is_ready)
704 DRM_ERROR("phylock is not ready!MIPIDSI_PHY_STATUS_OFFSET=0x%x.\n",
705 tmp);
706
707 if (lanes >= DSI_4_LANES)
708 cmp_stopstate_val = (BIT(4) | BIT(7) | BIT(9) | BIT(11));
709 else if (lanes >= DSI_3_LANES)
710 cmp_stopstate_val = (BIT(4) | BIT(7) | BIT(9));
711 else if (lanes >= DSI_2_LANES)
712 cmp_stopstate_val = (BIT(4) | BIT(7));
713 else
714 cmp_stopstate_val = (BIT(4));
715
716 is_ready = false;
717 dw_jiffies = jiffies + HZ / 2;
718 do {
719 tmp = readl(mipi_dsi_base + MIPIDSI_PHY_STATUS_OFFSET);
720 if ((tmp & cmp_stopstate_val) == cmp_stopstate_val) {
721 is_ready = true;
722 break;
723 }
724 } while (time_after(dw_jiffies, jiffies));
725
726 if (!is_ready)
727 DRM_ERROR("phystopstateclklane is not ready! MIPIDSI_PHY_STATUS_OFFSET=0x%x.\n",
728 tmp);
729
730 /*************************Configure the DPHY end*************************/
731
732 /* phy_stop_wait_time*/
733 set_reg(mipi_dsi_base + MIPIDSI_PHY_IF_CFG_OFFSET,
734 dsi->phy.phy_stop_wait_time, 8, 8);
735
736 /*--------------configuring the DPI packet transmission----------------*/
737 /*
738 * 2. Configure the DPI Interface:
739 * This defines how the DPI interface interacts with the controller.
740 */
741 set_reg(mipi_dsi_base + MIPIDSI_DPI_VCID_OFFSET, mipi->vc, 2, 0);
742 set_reg(mipi_dsi_base + MIPIDSI_DPI_COLOR_CODING_OFFSET,
743 mipi->color_mode, 4, 0);
744
745 set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET,
746 dsi->ldi.data_en_plr, 1, 0);
747 set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, dsi->ldi.vsync_plr,
748 1, 1);
749 set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, dsi->ldi.hsync_plr,
750 1, 2);
751 set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, 0x0, 1, 3);
752 set_reg(mipi_dsi_base + MIPIDSI_DPI_CFG_POL_OFFSET, 0x0, 1, 4);
753
754 /*
755 * 3. Select the Video Transmission Mode:
756 * This defines how the processor requires the video line to be
757 * transported through the DSI link.
758 */
759 /* video mode: low power mode*/
760 set_reg(mipi_dsi_base + MIPIDSI_VID_MODE_CFG_OFFSET, 0x3f, 6, 8);
761 /* set_reg(mipi_dsi_base + MIPIDSI_VID_MODE_CFG_OFFSET, 0x0, 1, 14); */
762
763 /* TODO: fix blank display bug when set backlight*/
764 set_reg(mipi_dsi_base + MIPIDSI_DPI_LP_CMD_TIM_OFFSET, 0x4, 8, 16);
765 /* video mode: send read cmd by lp mode*/
766 set_reg(mipi_dsi_base + MIPIDSI_VID_MODE_CFG_OFFSET, 0x1, 1, 15);
767
768 set_reg(mipi_dsi_base + MIPIDSI_VID_PKT_SIZE_OFFSET, rect.w, 14, 0);
769
770 /* burst mode*/
771 dsi_set_burst_mode(mipi_dsi_base, dsi->client[id].mode_flags);
772 /* for dsi read, BTA enable*/
773 set_reg(mipi_dsi_base + MIPIDSI_PCKHDL_CFG_OFFSET, 0x1, 1, 2);
774
775 /*
776 * 4. Define the DPI Horizontal timing configuration:
777 *
778 * Hsa_time = HSA*(PCLK period/Clk Lane Byte Period);
779 * Hbp_time = HBP*(PCLK period/Clk Lane Byte Period);
780 * Hline_time = (HSA+HBP+HACT+HFP)*(PCLK period/Clk Lane Byte Period);
781 */
782 pixel_clk = dsi->cur_mode.clock * 1000;
783 /*htot = dsi->cur_mode.htotal;*/
784 /*vtot = dsi->cur_mode.vtotal;*/
785 dsi->ldi.h_front_porch =
786 dsi->cur_mode.hsync_start - dsi->cur_mode.hdisplay;
787 dsi->ldi.h_back_porch = dsi->cur_mode.htotal - dsi->cur_mode.hsync_end;
788 dsi->ldi.h_pulse_width =
789 dsi->cur_mode.hsync_end - dsi->cur_mode.hsync_start;
790 dsi->ldi.v_front_porch =
791 dsi->cur_mode.vsync_start - dsi->cur_mode.vdisplay;
792 dsi->ldi.v_back_porch = dsi->cur_mode.vtotal - dsi->cur_mode.vsync_end;
793 dsi->ldi.v_pulse_width =
794 dsi->cur_mode.vsync_end - dsi->cur_mode.vsync_start;
795 if (dsi->ldi.v_pulse_width > 15) {
796 DRM_DEBUG_DRIVER("vsw exceeded 15\n");
797 dsi->ldi.v_pulse_width = 15;
798 }
799 hsa_time = dsi->ldi.h_pulse_width * dsi->phy.lane_byte_clk / pixel_clk;
800 hbp_time = dsi->ldi.h_back_porch * dsi->phy.lane_byte_clk / pixel_clk;
801 hline_time = DIV_ROUND_UP((dsi->ldi.h_pulse_width + dsi->ldi.h_back_porch +
802 rect.w + dsi->ldi.h_front_porch) *
803 dsi->phy.lane_byte_clk,
804 pixel_clk);
805
806 DRM_DEBUG("hsa_time=%d, hbp_time=%d, hline_time=%d\n", hsa_time,
807 hbp_time, hline_time);
808 DRM_DEBUG("lane_byte_clk=%llu, pixel_clk=%llu\n", dsi->phy.lane_byte_clk,
809 pixel_clk);
810 set_reg(mipi_dsi_base + MIPIDSI_VID_HSA_TIME_OFFSET, hsa_time, 12, 0);
811 set_reg(mipi_dsi_base + MIPIDSI_VID_HBP_TIME_OFFSET, hbp_time, 12, 0);
812 set_reg(mipi_dsi_base + MIPIDSI_VID_HLINE_TIME_OFFSET, hline_time, 15,
813 0);
814
815 /* Define the Vertical line configuration*/
816 set_reg(mipi_dsi_base + MIPIDSI_VID_VSA_LINES_OFFSET,
817 dsi->ldi.v_pulse_width, 10, 0);
818 set_reg(mipi_dsi_base + MIPIDSI_VID_VBP_LINES_OFFSET,
819 dsi->ldi.v_back_porch, 10, 0);
820 set_reg(mipi_dsi_base + MIPIDSI_VID_VFP_LINES_OFFSET,
821 dsi->ldi.v_front_porch, 10, 0);
822 set_reg(mipi_dsi_base + MIPIDSI_VID_VACTIVE_LINES_OFFSET, rect.h, 14,
823 0);
824 set_reg(mipi_dsi_base + MIPIDSI_TO_CNT_CFG_OFFSET, 0x7FF, 16, 0);
825
826 /* Configure core's phy parameters*/
827 set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET,
828 dsi->phy.clk_lane_lp2hs_time, 10, 0);
829 set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET,
830 dsi->phy.clk_lane_hs2lp_time, 10, 16);
831
832 set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_RD_CFG_OFFSET, 0x7FFF, 15, 0);
833 set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_CFG_OFFSET,
834 dsi->phy.data_lane_lp2hs_time, 10, 0);
835 set_reg(mipi_dsi_base + MIPIDSI_PHY_TMR_CFG_OFFSET,
836 dsi->phy.data_lane_hs2lp_time, 10, 16);
837
838 /* Waking up Core*/
839 set_reg(mipi_dsi_base + MIPIDSI_PWR_UP_OFFSET, 0x1, 1, 0);
840 }
841
mipi_dsi_on_sub1(struct dw_dsi * dsi,char __iomem * mipi_dsi_base)842 static int mipi_dsi_on_sub1(struct dw_dsi *dsi, char __iomem *mipi_dsi_base)
843 {
844 /* mipi init */
845 dsi_mipi_init(dsi, mipi_dsi_base);
846 DRM_DEBUG("dsi_mipi_init ok\n");
847 /* switch to cmd mode */
848 set_reg(mipi_dsi_base + MIPIDSI_MODE_CFG_OFFSET, 0x1, 1, 0);
849 /* cmd mode: low power mode */
850 set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0x7f, 7, 8);
851 set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0xf, 4, 16);
852 set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0x1, 1, 24);
853 /* disable generate High Speed clock */
854 /* delete? */
855 set_reg(mipi_dsi_base + MIPIDSI_LPCLK_CTRL_OFFSET, 0x0, 1, 0);
856
857 return 0;
858 }
859
mipi_dsi_on_sub2(struct dw_dsi * dsi,char __iomem * mipi_dsi_base)860 static int mipi_dsi_on_sub2(struct dw_dsi *dsi, char __iomem *mipi_dsi_base)
861 {
862 /* switch to video mode */
863 set_reg(mipi_dsi_base + MIPIDSI_MODE_CFG_OFFSET, 0x0, 1, 0);
864
865 /* enable EOTP TX */
866 set_reg(mipi_dsi_base + MIPIDSI_PCKHDL_CFG_OFFSET, 0x1, 1, 0);
867
868 /* enable generate High Speed clock, continue clock */
869 set_reg(mipi_dsi_base + MIPIDSI_LPCLK_CTRL_OFFSET, 0x1, 2, 0);
870
871 return 0;
872 }
873
dsi_encoder_enable_sub(struct drm_encoder * encoder)874 static void dsi_encoder_enable_sub(struct drm_encoder *encoder)
875 {
876 struct dw_dsi *dsi = encoder_to_dsi(encoder);
877 struct dsi_hw_ctx *ctx = dsi->ctx;
878 int ret;
879
880 if (dsi->enable)
881 return;
882
883 ret = clk_prepare_enable(ctx->dss_dphy0_ref_clk);
884 if (ret) {
885 DRM_ERROR("fail to enable dss_dphy0_ref_clk: %d\n", ret);
886 return;
887 }
888
889 ret = clk_prepare_enable(ctx->dss_dphy0_cfg_clk);
890 if (ret) {
891 DRM_ERROR("fail to enable dss_dphy0_cfg_clk: %d\n", ret);
892 return;
893 }
894
895 ret = clk_prepare_enable(ctx->dss_pclk_dsi0_clk);
896 if (ret) {
897 DRM_ERROR("fail to enable dss_pclk_dsi0_clk: %d\n", ret);
898 return;
899 }
900
901 mipi_dsi_on_sub1(dsi, ctx->base);
902
903 mipi_dsi_on_sub2(dsi, ctx->base);
904 }
905
dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * mdsi)906 static int dsi_host_attach(struct mipi_dsi_host *host,
907 struct mipi_dsi_device *mdsi)
908 {
909 struct dw_dsi *dsi = host_to_dsi(host);
910 u32 id = mdsi->channel >= 1 ? OUT_PANEL : OUT_HDMI;
911
912 if (mdsi->lanes < 1 || mdsi->lanes > 4) {
913 DRM_ERROR("dsi device params invalid\n");
914 return -EINVAL;
915 }
916
917 dsi->client[id].lanes = mdsi->lanes;
918 dsi->client[id].format = mdsi->format;
919 dsi->client[id].mode_flags = mdsi->mode_flags;
920 dsi->client[id].phy_clock = 0; //mdsi->phy_clock;
921
922 DRM_DEBUG("host attach, client name=[%s], id=%d\n", mdsi->name, id);
923
924 return 0;
925 }
926
dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * mdsi)927 static int dsi_host_detach(struct mipi_dsi_host *host,
928 struct mipi_dsi_device *mdsi)
929 {
930 /* do nothing */
931 return 0;
932 }
933
dsi_gen_pkt_hdr_write(void __iomem * base,u32 val)934 static int dsi_gen_pkt_hdr_write(void __iomem *base, u32 val)
935 {
936 u32 status;
937 int ret;
938
939 ret = readx_poll_timeout(readl, base + CMD_PKT_STATUS, status,
940 !(status & GEN_CMD_FULL), 1000,
941 CMD_PKT_STATUS_TIMEOUT_US);
942 if (ret < 0) {
943 DRM_ERROR("failed to get available command FIFO\n");
944 return ret;
945 }
946
947 writel(val, base + GEN_HDR);
948
949 ret = readx_poll_timeout(readl, base + CMD_PKT_STATUS, status,
950 status & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
951 1000, CMD_PKT_STATUS_TIMEOUT_US);
952 if (ret < 0) {
953 DRM_ERROR("failed to write command FIFO\n");
954 return ret;
955 }
956
957 return 0;
958 }
959
dsi_dcs_short_write(void __iomem * base,const struct mipi_dsi_msg * msg)960 static int dsi_dcs_short_write(void __iomem *base,
961 const struct mipi_dsi_msg *msg)
962 {
963 const u16 *tx_buf = msg->tx_buf;
964 u32 val = GEN_HDATA(*tx_buf) | GEN_HTYPE(msg->type);
965
966 if (msg->tx_len > 2) {
967 DRM_ERROR("too long tx buf length %zu for short write\n",
968 msg->tx_len);
969 return -EINVAL;
970 }
971
972 return dsi_gen_pkt_hdr_write(base, val);
973 }
974
dsi_dcs_long_write(void __iomem * base,const struct mipi_dsi_msg * msg)975 static int dsi_dcs_long_write(void __iomem *base,
976 const struct mipi_dsi_msg *msg)
977 {
978 const u32 *tx_buf = msg->tx_buf;
979 int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
980 u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
981 u32 remainder = 0;
982 u32 status;
983
984 if (msg->tx_len < 3) {
985 DRM_ERROR("wrong tx buf length %zu for long write\n",
986 msg->tx_len);
987 return -EINVAL;
988 }
989
990 while (DIV_ROUND_UP(len, pld_data_bytes)) {
991 if (len < pld_data_bytes) {
992 memcpy(&remainder, tx_buf, len);
993 writel(remainder, base + GEN_PLD_DATA);
994 len = 0;
995 } else {
996 writel(*tx_buf, base + GEN_PLD_DATA);
997 tx_buf++;
998 len -= pld_data_bytes;
999 }
1000
1001 ret = readx_poll_timeout(readl, base + CMD_PKT_STATUS, status,
1002 !(status & GEN_PLD_W_FULL), 1000,
1003 CMD_PKT_STATUS_TIMEOUT_US);
1004 if (ret < 0) {
1005 DRM_ERROR("failed to get available write payload FIFO\n");
1006 return ret;
1007 }
1008 }
1009
1010 return dsi_gen_pkt_hdr_write(base, val);
1011 }
1012
dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1013 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1014 const struct mipi_dsi_msg *msg)
1015 {
1016 struct dw_dsi *dsi = host_to_dsi(host);
1017 struct dsi_hw_ctx *ctx = dsi->ctx;
1018 void __iomem *base = ctx->base;
1019 int ret;
1020
1021 switch (msg->type) {
1022 case MIPI_DSI_DCS_SHORT_WRITE:
1023 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
1024 case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE:
1025 ret = dsi_dcs_short_write(base, msg);
1026 break;
1027 case MIPI_DSI_DCS_LONG_WRITE:
1028 ret = dsi_dcs_long_write(base, msg);
1029 break;
1030 default:
1031 DRM_ERROR("unsupported message type\n");
1032 ret = -EINVAL;
1033 }
1034
1035 return ret;
1036 }
1037
1038 static const struct mipi_dsi_host_ops dsi_host_ops = {
1039 .attach = dsi_host_attach,
1040 .detach = dsi_host_detach,
1041 .transfer = dsi_host_transfer,
1042 };
1043
dsi_host_init(struct device * dev,struct dw_dsi * dsi)1044 static int dsi_host_init(struct device *dev, struct dw_dsi *dsi)
1045 {
1046 struct mipi_dsi_host *host = &dsi->host;
1047 struct mipi_panel_info *mipi = &dsi->mipi;
1048 int ret;
1049
1050 host->dev = dev;
1051 host->ops = &dsi_host_ops;
1052
1053 mipi->max_tx_esc_clk = 10 * 1000000UL;
1054 mipi->vc = 0;
1055 mipi->color_mode = DSI_24BITS_1;
1056 mipi->clk_post_adjust = 120;
1057 mipi->clk_pre_adjust = 0;
1058 mipi->clk_t_hs_prepare_adjust = 0;
1059 mipi->clk_t_lpx_adjust = 0;
1060 mipi->clk_t_hs_trial_adjust = 0;
1061 mipi->clk_t_hs_exit_adjust = 0;
1062 mipi->clk_t_hs_zero_adjust = 0;
1063
1064 dsi->ldi.data_en_plr = 0;
1065 dsi->ldi.vsync_plr = 0;
1066 dsi->ldi.hsync_plr = 0;
1067
1068 ret = mipi_dsi_host_register(host);
1069 if (ret) {
1070 DRM_ERROR("failed to register dsi host\n");
1071 return ret;
1072 }
1073
1074 return 0;
1075 }
1076
dsi_parse_bridge_endpoint(struct dw_dsi * dsi,struct device_node * endpoint)1077 static int dsi_parse_bridge_endpoint(struct dw_dsi *dsi,
1078 struct device_node *endpoint)
1079 {
1080 struct device_node *bridge_node;
1081 struct drm_bridge *bridge;
1082
1083 bridge_node = of_graph_get_remote_port_parent(endpoint);
1084 if (!bridge_node) {
1085 DRM_ERROR("no valid bridge node\n");
1086 return -ENODEV;
1087 }
1088 of_node_put(bridge_node);
1089
1090 bridge = of_drm_find_bridge(bridge_node);
1091 if (!bridge) {
1092 DRM_DEBUG("wait for external HDMI bridge driver.\n");
1093 return -EPROBE_DEFER;
1094 }
1095 dsi->bridge = bridge;
1096
1097 return 0;
1098 }
1099
dsi_parse_panel_endpoint(struct dw_dsi * dsi,struct device_node * endpoint)1100 static int dsi_parse_panel_endpoint(struct dw_dsi *dsi,
1101 struct device_node *endpoint)
1102 {
1103 struct device_node *panel_node;
1104 struct drm_panel *panel;
1105
1106 panel_node = of_graph_get_remote_port_parent(endpoint);
1107 if (!panel_node) {
1108 DRM_ERROR("no valid panel node\n");
1109 return -ENODEV;
1110 }
1111 of_node_put(panel_node);
1112
1113 panel = of_drm_find_panel(panel_node);
1114 if (IS_ERR(panel)) {
1115 DRM_DEBUG_DRIVER("skip this panel endpoint.\n");
1116 return 0;
1117 }
1118 dsi->panel = panel;
1119
1120 return 0;
1121 }
1122
dsi_parse_endpoint(struct dw_dsi * dsi,struct device_node * np,enum dsi_output_client client)1123 static int dsi_parse_endpoint(struct dw_dsi *dsi, struct device_node *np,
1124 enum dsi_output_client client)
1125 {
1126 struct device_node *ep_node;
1127 struct of_endpoint ep;
1128 int ret = 0;
1129
1130 if (client == OUT_MAX)
1131 return -EINVAL;
1132
1133 for_each_endpoint_of_node(np, ep_node) {
1134 ret = of_graph_parse_endpoint(ep_node, &ep);
1135 if (ret) {
1136 of_node_put(ep_node);
1137 return ret;
1138 }
1139
1140 /* skip dsi input port, port == 0 is input port */
1141 if (ep.port == 0)
1142 continue;
1143
1144 /* parse bridge endpoint */
1145 if (client == OUT_HDMI) {
1146 if (ep.id == 0) {
1147 ret = dsi_parse_bridge_endpoint(dsi, ep_node);
1148 if (dsi->bridge)
1149 break;
1150 }
1151 } else { /* parse panel endpoint */
1152 if (ep.id > 0) {
1153 ret = dsi_parse_panel_endpoint(dsi, ep_node);
1154 if (dsi->panel)
1155 break;
1156 }
1157 }
1158
1159 if (ret) {
1160 of_node_put(ep_node);
1161 return ret;
1162 }
1163 }
1164
1165 if (!dsi->bridge && !dsi->panel) {
1166 DRM_ERROR("at least one bridge or panel node is required\n");
1167 return -ENODEV;
1168 }
1169
1170 return 0;
1171 }
1172
dsi_parse_dt(struct platform_device * pdev,struct dw_dsi * dsi)1173 static int dsi_parse_dt(struct platform_device *pdev, struct dw_dsi *dsi)
1174 {
1175 struct dsi_hw_ctx *ctx = dsi->ctx;
1176 int ret = 0;
1177 struct device_node *np = pdev->dev.of_node;
1178
1179 /* parse HDMI bridge endpoint */
1180 ret = dsi_parse_endpoint(dsi, np, OUT_HDMI);
1181 if (ret)
1182 return ret;
1183
1184 /* parse panel endpoint */
1185 ret = dsi_parse_endpoint(dsi, np, OUT_PANEL);
1186 if (ret)
1187 return ret;
1188
1189 np = of_find_compatible_node(NULL, NULL, DTS_COMP_DSI_NAME);
1190 if (!np) {
1191 DRM_ERROR("NOT FOUND device node %s!\n", DTS_COMP_DSI_NAME);
1192 return -ENXIO;
1193 }
1194
1195 ctx->base = of_iomap(np, 0);
1196 if (!(ctx->base)) {
1197 DRM_ERROR("failed to get base resource.\n");
1198 return -ENXIO;
1199 }
1200
1201 ctx->peri_crg_base = of_iomap(np, 1);
1202 if (!(ctx->peri_crg_base)) {
1203 DRM_ERROR("failed to get peri_crg_base resource.\n");
1204 return -ENXIO;
1205 }
1206
1207 dsi->gpio_mux = devm_gpiod_get(&pdev->dev, "mux", GPIOD_OUT_HIGH);
1208 if (IS_ERR(dsi->gpio_mux))
1209 return PTR_ERR(dsi->gpio_mux);
1210 /* set dsi default output to panel */
1211 dsi->cur_client = OUT_PANEL;
1212
1213 /*dis-reset*/
1214 /*ip_reset_dis_dsi0, ip_reset_dis_dsi1*/
1215 writel(0x30000000, ctx->peri_crg_base + PERRSTDIS3);
1216
1217 ctx->dss_dphy0_ref_clk = devm_clk_get(&pdev->dev, "clk_txdphy0_ref");
1218 if (IS_ERR(ctx->dss_dphy0_ref_clk)) {
1219 DRM_ERROR("failed to get dss_dphy0_ref_clk clock\n");
1220 return PTR_ERR(ctx->dss_dphy0_ref_clk);
1221 }
1222
1223 ret = clk_set_rate(ctx->dss_dphy0_ref_clk, DEFAULT_MIPI_CLK_RATE);
1224 if (ret < 0) {
1225 DRM_ERROR("dss_dphy0_ref_clk clk_set_rate(%lu) failed, error=%d!\n",
1226 DEFAULT_MIPI_CLK_RATE, ret);
1227 return -EINVAL;
1228 }
1229
1230 DRM_DEBUG("dss_dphy0_ref_clk:[%lu]->[%lu].\n", DEFAULT_MIPI_CLK_RATE,
1231 clk_get_rate(ctx->dss_dphy0_ref_clk));
1232
1233 ctx->dss_dphy0_cfg_clk = devm_clk_get(&pdev->dev, "clk_txdphy0_cfg");
1234 if (IS_ERR(ctx->dss_dphy0_cfg_clk)) {
1235 DRM_ERROR("failed to get dss_dphy0_cfg_clk clock\n");
1236 return PTR_ERR(ctx->dss_dphy0_cfg_clk);
1237 }
1238
1239 ret = clk_set_rate(ctx->dss_dphy0_cfg_clk, DEFAULT_MIPI_CLK_RATE);
1240 if (ret < 0) {
1241 DRM_ERROR(
1242 "dss_dphy0_cfg_clk clk_set_rate(%lu) failed, error=%d!\n",
1243 DEFAULT_MIPI_CLK_RATE, ret);
1244 return -EINVAL;
1245 }
1246
1247 DRM_DEBUG("dss_dphy0_cfg_clk:[%lu]->[%lu].\n", DEFAULT_MIPI_CLK_RATE,
1248 clk_get_rate(ctx->dss_dphy0_cfg_clk));
1249
1250 ctx->dss_pclk_dsi0_clk = devm_clk_get(&pdev->dev, "pclk_dsi0");
1251 if (IS_ERR(ctx->dss_pclk_dsi0_clk)) {
1252 DRM_ERROR("failed to get dss_pclk_dsi0_clk clock\n");
1253 return PTR_ERR(ctx->dss_pclk_dsi0_clk);
1254 }
1255
1256 return 0;
1257 }
1258
1259 const struct kirin_dsi_ops kirin_dsi_960 = {
1260 .version = KIRIN960_DSI,
1261 .parse_dt = dsi_parse_dt,
1262 .host_init = dsi_host_init,
1263 .encoder_enable = dsi_encoder_enable_sub,
1264 .encoder_valid = dsi_encoder_mode_valid
1265 };
1266
1267 MODULE_DESCRIPTION("DesignWare MIPI DSI Host Controller v1.02 driver");
1268 MODULE_LICENSE("GPL v2");
1269