1/* 2 * clock specification for Xilinx ZynqMP ep108 development board 3 * 4 * (C) Copyright 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11&amba { 12 misc_clk: misc_clk { 13 compatible = "fixed-clock"; 14 #clock-cells = <0>; 15 clock-frequency = <25000000>; 16 u-boot,dm-pre-reloc; 17 }; 18 19 i2c_clk: i2c_clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0x0>; 22 clock-frequency = <111111111>; 23 }; 24 25 sata_clk: sata_clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 clock-frequency = <75000000>; 29 }; 30 31 dp_aclk: clock0 { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <50000000>; 35 clock-accuracy = <100>; 36 }; 37 38 clk100: clk100 { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 clock-frequency = <100000000>; 42 }; 43 44 clk600: clk600 { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <600000000>; 48 }; 49 50 dp_aud_clk: clock1 { 51 compatible = "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <22579200>; 54 clock-accuracy = <100>; 55 }; 56}; 57 58&can0 { 59 clocks = <&misc_clk &misc_clk>; 60}; 61 62&can1 { 63 clocks = <&misc_clk &misc_clk>; 64}; 65 66&fpd_dma_chan1 { 67 clocks = <&clk600>, <&clk100>; 68}; 69 70&fpd_dma_chan2 { 71 clocks = <&clk600>, <&clk100>; 72}; 73 74&fpd_dma_chan3 { 75 clocks = <&clk600>, <&clk100>; 76}; 77 78&fpd_dma_chan4 { 79 clocks = <&clk600>, <&clk100>; 80}; 81 82&fpd_dma_chan5 { 83 clocks = <&clk600>, <&clk100>; 84}; 85 86&fpd_dma_chan6 { 87 clocks = <&clk600>, <&clk100>; 88}; 89 90&fpd_dma_chan7 { 91 clocks = <&clk600>, <&clk100>; 92}; 93 94&fpd_dma_chan8 { 95 clocks = <&clk600>, <&clk100>; 96}; 97 98&gem0 { 99 clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>; 100}; 101 102&gpio { 103 clocks = <&misc_clk>; 104}; 105 106&i2c0 { 107 clocks = <&i2c_clk>; 108}; 109 110&i2c1 { 111 clocks = <&i2c_clk>; 112}; 113 114&nand0 { 115 clocks = <&misc_clk &misc_clk>; 116}; 117 118&qspi { 119 clocks = <&misc_clk &misc_clk>; 120}; 121 122&sata { 123 clocks = <&sata_clk>; 124}; 125 126&sdhci0 { 127 clocks = <&misc_clk>, <&misc_clk>; 128}; 129 130&sdhci1 { 131 clocks = <&misc_clk>, <&misc_clk>; 132}; 133 134&spi0 { 135 clocks = <&misc_clk &misc_clk>; 136}; 137 138&spi1 { 139 clocks = <&misc_clk &misc_clk>; 140}; 141 142&uart0 { 143 clocks = <&misc_clk &misc_clk>; 144}; 145 146&usb0 { 147 clocks = <&misc_clk>, <&misc_clk>; 148}; 149 150&usb1 { 151 clocks = <&misc_clk>, <&misc_clk>; 152}; 153 154&watchdog0 { 155 clocks= <&misc_clk>; 156}; 157 158&xilinx_drm { 159 clocks = <&misc_clk>; 160}; 161 162&xlnx_dp { 163 clocks = <&dp_aclk>, <&dp_aud_clk>; 164}; 165 166&xlnx_dp_snd_codec0 { 167 clocks = <&dp_aud_clk>; 168}; 169 170&xlnx_dpdma { 171 clocks = <&misc_clk>; 172}; 173