1*4882a593Smuzhiyunconfig CLK_AT91 2*4882a593Smuzhiyun bool "AT91 clock drivers" 3*4882a593Smuzhiyun depends on CLK 4*4882a593Smuzhiyun select MISC 5*4882a593Smuzhiyun help 6*4882a593Smuzhiyun This option is used to enable the AT91 clock driver. 7*4882a593Smuzhiyun The driver supports the AT91 clock generator, including 8*4882a593Smuzhiyun the oscillators and PLLs, such as main clock, slow clock, 9*4882a593Smuzhiyun PLLA, UTMI PLL. Clocks can also be a source clock of other 10*4882a593Smuzhiyun clocks a tree structure, such as master clock, usb device 11*4882a593Smuzhiyun clock, matrix clock and generic clock. 12*4882a593Smuzhiyun Devices can use a common clock API to request a particular 13*4882a593Smuzhiyun clock, enable it and get its rate. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunconfig AT91_UTMI 16*4882a593Smuzhiyun bool "Support UTMI PLL Clock" 17*4882a593Smuzhiyun depends on CLK_AT91 18*4882a593Smuzhiyun help 19*4882a593Smuzhiyun This option is used to enable the AT91 UTMI PLL clock 20*4882a593Smuzhiyun driver. It is the clock provider of USB, and UPLLCK is the 21*4882a593Smuzhiyun output of 480 MHz UTMI PLL, The souce clock of the UTMI 22*4882a593Smuzhiyun PLL is the main clock, so the main clock must select the 23*4882a593Smuzhiyun fast crystal oscillator to meet the frequency accuracy 24*4882a593Smuzhiyun required by USB. 25*4882a593Smuzhiyun 26*4882a593Smuzhiyunconfig AT91_H32MX 27*4882a593Smuzhiyun bool "Support H32MX 32-bit Matrix Clock" 28*4882a593Smuzhiyun depends on CLK_AT91 29*4882a593Smuzhiyun help 30*4882a593Smuzhiyun This option is used to enable the AT91 H32MX matrixes 31*4882a593Smuzhiyun clock driver. There are H64MX and H32MX matrixes clocks, 32*4882a593Smuzhiyun H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit 33*4882a593Smuzhiyun matrix clock is to be configured as MCK if MCK does not 34*4882a593Smuzhiyun exceed 83 MHz, else it is to be configured as MCK/2. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunconfig AT91_GENERIC_CLK 37*4882a593Smuzhiyun bool "Support Generic Clock" 38*4882a593Smuzhiyun depends on CLK_AT91 39*4882a593Smuzhiyun help 40*4882a593Smuzhiyun This option is used to enable the AT91 generic clock 41*4882a593Smuzhiyun driver. Some peripherals may need a second clock source 42*4882a593Smuzhiyun that may be different from the system clock. This second 43*4882a593Smuzhiyun clock is the generic clock (GCLK) and is managed by 44*4882a593Smuzhiyun the PMC via PMC_PCR register. 45