xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/zynqmp-ep108-clk.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun/*
2*4882a593Smuzhiyun * clock specification for Xilinx ZynqMP ep108 development board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2015, Xilinx, Inc.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Michal Simek <michal.simek@xilinx.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier:	GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun&amba {
12*4882a593Smuzhiyun	misc_clk: misc_clk {
13*4882a593Smuzhiyun		compatible = "fixed-clock";
14*4882a593Smuzhiyun		#clock-cells = <0>;
15*4882a593Smuzhiyun		clock-frequency = <25000000>;
16*4882a593Smuzhiyun		u-boot,dm-pre-reloc;
17*4882a593Smuzhiyun	};
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun	i2c_clk: i2c_clk {
20*4882a593Smuzhiyun		compatible = "fixed-clock";
21*4882a593Smuzhiyun		#clock-cells = <0x0>;
22*4882a593Smuzhiyun		clock-frequency = <111111111>;
23*4882a593Smuzhiyun	};
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun	sata_clk: sata_clk {
26*4882a593Smuzhiyun		compatible = "fixed-clock";
27*4882a593Smuzhiyun		#clock-cells = <0>;
28*4882a593Smuzhiyun		clock-frequency = <75000000>;
29*4882a593Smuzhiyun	};
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun	dp_aclk: clock0 {
32*4882a593Smuzhiyun		compatible = "fixed-clock";
33*4882a593Smuzhiyun		#clock-cells = <0>;
34*4882a593Smuzhiyun		clock-frequency = <50000000>;
35*4882a593Smuzhiyun		clock-accuracy = <100>;
36*4882a593Smuzhiyun	};
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun	clk100: clk100 {
39*4882a593Smuzhiyun		compatible = "fixed-clock";
40*4882a593Smuzhiyun		#clock-cells = <0>;
41*4882a593Smuzhiyun		clock-frequency = <100000000>;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	clk600: clk600 {
45*4882a593Smuzhiyun		compatible = "fixed-clock";
46*4882a593Smuzhiyun		#clock-cells = <0>;
47*4882a593Smuzhiyun		clock-frequency = <600000000>;
48*4882a593Smuzhiyun	};
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun	dp_aud_clk: clock1 {
51*4882a593Smuzhiyun		compatible = "fixed-clock";
52*4882a593Smuzhiyun		#clock-cells = <0>;
53*4882a593Smuzhiyun		clock-frequency = <22579200>;
54*4882a593Smuzhiyun		clock-accuracy = <100>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun};
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun&can0 {
59*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
60*4882a593Smuzhiyun};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun&can1 {
63*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
64*4882a593Smuzhiyun};
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun&fpd_dma_chan1 {
67*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
68*4882a593Smuzhiyun};
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun&fpd_dma_chan2 {
71*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
72*4882a593Smuzhiyun};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun&fpd_dma_chan3 {
75*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
76*4882a593Smuzhiyun};
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun&fpd_dma_chan4 {
79*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
80*4882a593Smuzhiyun};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun&fpd_dma_chan5 {
83*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
84*4882a593Smuzhiyun};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun&fpd_dma_chan6 {
87*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun&fpd_dma_chan7 {
91*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
92*4882a593Smuzhiyun};
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun&fpd_dma_chan8 {
95*4882a593Smuzhiyun	clocks = <&clk600>, <&clk100>;
96*4882a593Smuzhiyun};
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun&gem0 {
99*4882a593Smuzhiyun	clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
100*4882a593Smuzhiyun};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun&gpio {
103*4882a593Smuzhiyun	clocks = <&misc_clk>;
104*4882a593Smuzhiyun};
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun&i2c0 {
107*4882a593Smuzhiyun	clocks = <&i2c_clk>;
108*4882a593Smuzhiyun};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun&i2c1 {
111*4882a593Smuzhiyun	clocks = <&i2c_clk>;
112*4882a593Smuzhiyun};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun&nand0 {
115*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
116*4882a593Smuzhiyun};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun&qspi {
119*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
120*4882a593Smuzhiyun};
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun&sata {
123*4882a593Smuzhiyun	clocks = <&sata_clk>;
124*4882a593Smuzhiyun};
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun&sdhci0 {
127*4882a593Smuzhiyun	clocks = <&misc_clk>, <&misc_clk>;
128*4882a593Smuzhiyun};
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun&sdhci1 {
131*4882a593Smuzhiyun	clocks = <&misc_clk>, <&misc_clk>;
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&spi0 {
135*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&spi1 {
139*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&uart0 {
143*4882a593Smuzhiyun	clocks = <&misc_clk &misc_clk>;
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&usb0 {
147*4882a593Smuzhiyun	clocks = <&misc_clk>, <&misc_clk>;
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&usb1 {
151*4882a593Smuzhiyun	clocks = <&misc_clk>, <&misc_clk>;
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&watchdog0 {
155*4882a593Smuzhiyun	clocks= <&misc_clk>;
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&xilinx_drm {
159*4882a593Smuzhiyun	clocks = <&misc_clk>;
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&xlnx_dp {
163*4882a593Smuzhiyun	clocks = <&dp_aclk>, <&dp_aud_clk>;
164*4882a593Smuzhiyun};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun&xlnx_dp_snd_codec0 {
167*4882a593Smuzhiyun	clocks = <&dp_aud_clk>;
168*4882a593Smuzhiyun};
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun&xlnx_dpdma {
171*4882a593Smuzhiyun	clocks = <&misc_clk>;
172*4882a593Smuzhiyun};
173