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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Ds3c64xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/clk.h>
58 old_freq = clk_get_rate(policy->clk) / 1000; in s3c64xx_cpufreq_set_target()
59 new_freq = s3c64xx_freq_table[index].frequency; in s3c64xx_cpufreq_set_target()
65 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
66 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
75 ret = clk_set_rate(policy->clk, new_freq * 1000); in s3c64xx_cpufreq_set_target()
85 dvfs->vddarm_min, in s3c64xx_cpufreq_set_target()
86 dvfs->vddarm_max); in s3c64xx_cpufreq_set_target()
90 if (clk_set_rate(policy->clk, old_freq * 1000) < 0) in s3c64xx_cpufreq_set_target()
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H A Ds3c24xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
7 * S3C24XX CPU Frequency scaling
18 #include <linux/clk.h>
24 #include <linux/soc/samsung/s3c-cpufreq-core.h>
25 #include <linux/soc/samsung/s3c-pm.h>
39 static struct clk *_clk_mpll;
40 static struct clk *_clk_xtal;
41 static struct clk *clk_fclk;
42 static struct clk *clk_hclk;
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H A Dvexpress-spc-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013 - 2019 ARM Ltd.
14 #include <linux/clk.h>
51 static struct clk *clk[MAX_CLUSTERS]; variable
56 static unsigned int clk_little_max; /* Maximum clock frequency (Little) */
93 u32 rate = clk_get_rate(clk[cur_cluster]) / 1000; in clk_get_cpu_rate()
130 ret = clk_set_rate(clk[new_cluster], new_rate * 1000); in ve_spc_cpufreq_set_rate()
136 * current design of the clk core layer. To work around this in ve_spc_cpufreq_set_rate()
138 * correct. This needs to be removed once clk core is fixed. in ve_spc_cpufreq_set_rate()
140 if (clk_get_rate(clk[new_cluster]) != new_rate * 1000) in ve_spc_cpufreq_set_rate()
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H A Ds3c2416-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <linux/clk.h>
25 struct clk *armdiv;
26 struct clk *armclk;
27 struct clk *hclk;
47 /* pseudo-frequency for dvs mode */
50 /* frequency to sleep and reboot in
61 /* S3C2416 only supports changing the voltage in the dvs-mode.
94 /* return our pseudo-frequency when in dvs mode */ in s3c2416_cpufreq_get_speed()
95 if (s3c_freq->is_dvs) in s3c2416_cpufreq_get_speed()
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H A Darmada-37xx-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0+
3 * CPU frequency scaling support for Armada 37xx platform.
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
10 #include <linux/clk.h>
26 #include "cpufreq-dt.h"
28 /* Clk register set */
124 pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000); in armada_37xx_cpu_freq_info_get()
166 * Set cpu divider based on the pre-computed array in in armada37xx_cpufreq_dvfs_setup()
186 * Find out the armada 37x supported AVS value whose voltage value is
187 * the round-up closest to the target voltage value.
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
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/OK3568_Linux_fs/kernel/arch/arm/kernel/
H A Dsmp_twd.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
28 static struct clk *twd_clk;
37 static int twd_shutdown(struct clock_event_device *clk) in twd_shutdown() argument
43 static int twd_set_oneshot(struct clock_event_device *clk) in twd_set_oneshot() argument
51 static int twd_set_periodic(struct clock_event_device *clk) in twd_set_periodic() argument
94 struct clock_event_device *clk = raw_cpu_ptr(twd_evt); in twd_timer_stop() local
96 twd_shutdown(clk); in twd_timer_stop()
97 disable_percpu_irq(clk->irq); in twd_timer_stop()
101 * Updates clockevent frequency when the cpu frequency changes.
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgm20b.c19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 #include <subdev/clk.h>
89 #define DFS_DET_RANGE 6 /* -2^6 ... 2^6-1 */
90 #define SDM_DIN_RANGE 12 /* -2^12 ... 2^12-1 */
99 .coeff_slope = -165230,
136 /* safe frequency we can use at minimum voltage */
160 gm20b_pllg_read_mnp(struct gm20b_clk *clk, struct gm20b_pll *pll) in gm20b_pllg_read_mnp() argument
162 struct nvkm_subdev *subdev = &clk->base.base.subdev; in gm20b_pllg_read_mnp()
163 struct nvkm_device *device = subdev->device; in gm20b_pllg_read_mnp()
166 gk20a_pllg_read_mnp(&clk->base, &pll->base); in gm20b_pllg_read_mnp()
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
22 #include <linux/clk.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
111 struct clk *clk; member
127 .name = "s3c2410-i2c",
130 .name = "s3c2440-i2c",
133 .name = "s3c2440-hdmiphy-i2c",
143 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
144 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
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H A Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
50 struct clk *clk; member
51 unsigned int frequency; member
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
88 writeb_relaxed(data, i2c->regs + II_DATA); in dc_i2c_data()
99 dc_i2c_write_byte(i2c, i2c->msg->buf[i2c->msgbuf_ptr++]); in dc_i2c_write_buf()
104 bool last = (i2c->msgbuf_ptr + 1 == i2c->msg->len); in dc_i2c_next_read()
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/OK3568_Linux_fs/kernel/drivers/sh/clk/
H A Dcore.c4 * Copyright (C) 2005 - 2010 Paul Mundt
8 * Copyright (C) 2004 - 2008 Nokia Corporation
29 #include <linux/clk.h>
39 void clk_rate_table_build(struct clk *clk, in clk_rate_table_build() argument
49 clk->nr_freqs = nr_freqs; in clk_rate_table_build()
55 if (src_table->divisors && i < src_table->nr_divisors) in clk_rate_table_build()
56 div = src_table->divisors[i]; in clk_rate_table_build()
58 if (src_table->multipliers && i < src_table->nr_multipliers) in clk_rate_table_build()
59 mult = src_table->multipliers[i]; in clk_rate_table_build()
64 freq = clk->parent->rate * mult / div; in clk_rate_table_build()
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/OK3568_Linux_fs/u-boot/drivers/spi/
H A Drk_spi.c6 * (C) Copyright 2008-2013 Rockchip Electronics
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <clk.h>
15 #include <dt-structs.h>
38 s32 frequency; /* Default clock frequency, -1 for none */ member
46 struct clk clk; member
67 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
68 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1)); in rkspi_dump_regs()
69 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr)); in rkspi_dump_regs()
70 debug("ser: \t\t0x%08x\n", readl(&regs->ser)); in rkspi_dump_regs()
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/OK3568_Linux_fs/kernel/drivers/clocksource/
H A Darm_arch_timer.c1 // SPDX-License-Identifier: GPL-2.0-only
93 struct clock_event_device *clk) in arch_timer_reg_write() argument
96 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
99 writel_relaxed(val, timer->base + CNTP_CTL); in arch_timer_reg_write()
102 writel_relaxed(val, timer->base + CNTP_TVAL); in arch_timer_reg_write()
106 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_write()
109 writel_relaxed(val, timer->base + CNTV_CTL); in arch_timer_reg_write()
112 writel_relaxed(val, timer->base + CNTV_TVAL); in arch_timer_reg_write()
122 struct clock_event_device *clk) in arch_timer_reg_read() argument
127 struct arch_timer *timer = to_arch_timer(clk); in arch_timer_reg_read()
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H A Dmps2-timer.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
51 writel_relaxed(val, to_mps2_clkevt(c)->reg + offset); in clockevent_mps2_writel()
72 u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick; in mps2_timer_set_periodic()
84 u32 status = readl_relaxed(ce->reg + TIMER_INT); in mps2_timer_interrupt()
91 writel_relaxed(1, ce->reg + TIMER_INT); in mps2_timer_interrupt()
93 ce->clkevt.event_handler(&ce->clkevt); in mps2_timer_interrupt()
101 struct clk *clk = NULL; in mps2_clockevent_init() local
105 const char *name = "mps2-clkevt"; in mps2_clockevent_init()
107 ret = of_property_read_u32(np, "clock-frequency", &rate); in mps2_clockevent_init()
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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c4 * SPDX-License-Identifier: GPL-2.0
73 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
82 * Desc: Finds CPU/DDR frequency ratio according to Sample@reset and table.
83 * Args: target_freq - target frequency
85 * Returns: freq_par - the ratio parameter
96 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
109 * Args: freq - target frequency
111 * Returns: MV_OK - success, MV_FAIL - fail
120 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
123 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
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/OK3568_Linux_fs/kernel/drivers/pwm/
H A Dpwm-brcmstb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/clk.h>
41 * Maximum control word value allowed when variable-frequency PWM is used as a
42 * clock for the constant-frequency PMW.
57 struct clk *clk; member
65 return __raw_readl(p->base + offset); in brcmstb_pwm_readl()
67 return readl_relaxed(p->base + offset); in brcmstb_pwm_readl()
74 __raw_writel(value, p->base + offset); in brcmstb_pwm_writel()
76 writel_relaxed(value, p->base + offset); in brcmstb_pwm_writel()
85 * Fv is derived from the variable frequency output. The variable frequency
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr_smu_msg.c19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 CTX->logger
65 } while (max_retries--); in dcn30_smu_wait_for_response()
199 /* Returns the actual frequency that was set in MHz, 0 on failure */
200 unsigned int dcn30_smu_set_hard_min_by_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, uint16_t… in dcn30_smu_set_hard_min_by_freq() argument
204 /* bits 23:16 for clock type, lower 16 bits for frequency in MHz */ in dcn30_smu_set_hard_min_by_freq()
205 uint32_t param = (clk << 16) | freq_mhz; in dcn30_smu_set_hard_min_by_freq()
207 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); in dcn30_smu_set_hard_min_by_freq()
212 smu_print("SMU Frequency set = %d MHz\n", response); in dcn30_smu_set_hard_min_by_freq()
217 /* Returns the actual frequency that was set in MHz, 0 on failure */
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/OK3568_Linux_fs/kernel/sound/soc/sh/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
7 #include <linux/clk-provider.h>
29 struct clk *clk[CLKMAX]; member
30 struct clk *clkout[CLKOUTMAX];
49 ((pos) = adg->clk[i]); \
54 ((pos) = adg->clkout[i]); \
56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg)
72 for (i = 3; i >= 0; i--) { in rsnd_adg_calculate_rbgx()
75 return (u32)((i << 8) | ((div / ratio) - 1)); in rsnd_adg_calculate_rbgx()
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/OK3568_Linux_fs/kernel/drivers/clk/sunxi-ng/
H A Dccu_mux.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk.h>
8 #include <linux/clk-provider.h>
22 if (!((common->features & CCU_FEATURE_FIXED_PREDIV) || in ccu_mux_get_prediv()
23 (common->features & CCU_FEATURE_VARIABLE_PREDIV) || in ccu_mux_get_prediv()
24 (common->features & CCU_FEATURE_ALL_PREDIV))) in ccu_mux_get_prediv()
27 if (common->features & CCU_FEATURE_ALL_PREDIV) in ccu_mux_get_prediv()
28 return common->prediv; in ccu_mux_get_prediv()
30 reg = readl(common->base + common->reg); in ccu_mux_get_prediv()
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/OK3568_Linux_fs/kernel/drivers/spi/
H A Dspi-rockchip-sfc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2017-2021, Rockchip Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 * Jon Lin <Jon.lin@rock-chips.com>
13 #include <linux/clk.h>
15 #include <linux/dma-mapping.h>
25 #include <linux/spi/spi-mem.h>
159 * devices (0-3), however I have only been able to test a single CS (CS 0)
184 struct clk *hclk;
185 struct clk *clk; member
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/OK3568_Linux_fs/kernel/drivers/clk/at91/
H A Ddt-compat.c1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/clk-provider.h>
3 #include <linux/clk/at91_pmc.h>
31 const char *name = np->name; in of_sama5d2_clk_audio_pll_frac_setup()
48 "atmel,sama5d2-clk-audio-pll-frac",
54 const char *name = np->name; in of_sama5d2_clk_audio_pll_pad_setup()
71 "atmel,sama5d2-clk-audio-pll-pad",
77 const char *name = np->name; in of_sama5d2_clk_audio_pll_pmc_setup()
94 "atmel,sama5d2-clk-audio-pll-pmc",
148 if (of_property_read_string(np, "clock-output-names", &name)) in of_sama5d2_clk_generated_setup()
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Drockchip,clk-out.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/rockchip,clk-out.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip Clock Out Control Module Binding
10 - Sugar Zhang <sugar.zhang@rock-chips.com>
13 This add support switch for clk-bidirection which located
14 at GRF, such as SAIx_MCLK_{IN OUT} which share the same pin.
16 which hard to addressed in one single clk driver. so, we add
20 clk usage (avoid high freq glitch), we set all clk out as disabled
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dmps2.dtsi6 * This file is dual-licensed: you can use it either under the terms
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 #include "armv7-m.dtsi"
48 #address-cells = <1>;
49 #size-cells = <1>;
51 oscclk0: clk-osc0 {
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <50000000>;
57 oscclk1: clk-osc1 {
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/OK3568_Linux_fs/u-boot/drivers/crypto/rockchip/
H A Dcrypto_v1.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <clk.h>
29 struct clk clk; member
32 u32 frequency; member
52 struct rk_crypto_reg *reg = priv->reg; in rk_hash_direct_calc()
55 return -EINVAL; in rk_hash_direct_calc()
61 writel(HASH_DONE_INT, &reg->crypto_intsts); in rk_hash_direct_calc()
64 writel((u32)(ulong)data, &reg->crypto_hrdmas); in rk_hash_direct_calc()
65 writel((data_len + 3) >> 2, &reg->crypto_hrdmal); in rk_hash_direct_calc()
68 rk_setreg(&reg->crypto_ctrl, HASH_START); in rk_hash_direct_calc()
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/OK3568_Linux_fs/kernel/drivers/clk/ti/
H A Ddpll44xx.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OMAP4-specific DPLL control functions
11 #include <linux/clk.h>
14 #include <linux/clk/ti.h>
19 * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that
20 * can supported when using the DPLL low-power mode. Frequencies are
22 * Status, and Low-Power Operation Mode".
37 static void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) in omap4_dpllmx_allow_gatectrl() argument
42 if (!clk) in omap4_dpllmx_allow_gatectrl()
45 mask = clk->flags & CLOCK_CLKOUTX2 ? in omap4_dpllmx_allow_gatectrl()
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