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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dxilinx.yaml7 title: Xilinx Zynq Platforms Device Tree Bindings
13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC
23 - digilent,zynq-zybo
24 - digilent,zynq-zybo-z7
25 - xlnx,zynq-cc108
26 - xlnx,zynq-zc702
27 - xlnx,zynq-zc706
28 - xlnx,zynq-zc770-xm010
29 - xlnx,zynq-zc770-xm011
30 - xlnx,zynq-zc770-xm012
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.zynq2 # Xilinx ZYNQ U-Boot
11 This document describes the information about Xilinx Zynq U-Boot -
14 2. Zynq boards
16 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level
38 Zynq has a facility to read the bootmode from the slcr bootmode register
59 - Added zynq u-boot bsp code - arch/arm/cpu/armv7/zynq
60 - Added zynq boards named - zc70x, zed, microzed, zc770_xm010, zc770_xm012, zc770_xm013
61 - Added zynq drivers:
70 - Added basic FDT support for zynq boards
75 - Add zynq boards support - zc770_xm011
[all …]
/OK3568_Linux_fs/buildroot/board/zynqmp/patches/uboot/
H A D0004-arm-arm64-zynq-zynqmp-pass-the-PS-init-file-as-a-kco.patch4 Subject: [PATCH] arm/arm64: zynq/zynqmp: pass the PS init file as a kconfig
7 U-Boot needs to link ps7_init_gpl.c on Zynq or psu_init_gpl.c on
12 board/xilinx/zynq[mp]/$(CONFIG_DEFAULT_DEVICE_TREE)/ps?_init_gpl.c
14 2. otherwise use board/xilinx/zynq/ps?_init_gpl.c
39 Since the issue is the same for Zynq and ZynqMP, add one kconfig
46 - platform: zynq or zynqmp
48 non-existing), in-tree board-specific, in board/xilinx/zynq[mp]/
51 …4cc7fe5c4881589d5e440a17cb51fc66a7ab/meta-xilinx-bsp/recipes-bsp/u-boot/u-boot-spl-zynq-init.inc#L9
61 board/xilinx/zynq/Makefile | 10 +++++++++-
91 + string "Zynq/ZynqMP PS init file(s) location"
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt1 Xilinx Zynq Reset Manager
3 The Zynq AP-SoC has several different resets.
5 See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets.
8 - compatible: "xlnx,zynq-reset"
11 This should be a phandle to the Zynq's SLCR registers.
14 The Zynq Reset Manager needs to be a childnode of the SLCR.
18 compatible = "xlnx,zynq-reset";
H A Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC and Versal reset driver binding =
4 The Zynq UltraScale+ MPSoC and Versal has several different resets.
6 See Chapter 36 of the Zynq UltraScale+ MPSoC TRM (UG) for more information
13 - compatible: "xlnx,zynqmp-reset" for Zynq UltraScale+ MPSoC platform
41 For list of all valid reset indices for Zynq UltraScale+ MPSoC see
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi2 * Xilinx Zynq 7000 DTSI
3 * Describes the hardware common to all Zynq 7000-based boards.
13 compatible = "xlnx,zynq-7000";
74 compatible = "xlnx,zynq-xadc-1.00.a";
82 compatible = "xlnx,zynq-can-1.0";
94 compatible = "xlnx,zynq-can-1.0";
106 compatible = "xlnx,zynq-gpio-1.0";
158 compatible = "xlnx,zynq-ddrc-a05";
181 compatible = "xlnx,zynq-spi-r1p6";
193 compatible = "xlnx,zynq-spi-r1p6";
[all …]
H A DMakefile130 dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
131 zynq-zc706.dtb \
132 zynq-zed.dtb \
133 zynq-zybo.dtb \
134 zynq-microzed.dtb \
135 zynq-picozed.dtb \
136 zynq-topic-miami.dtb \
137 zynq-topic-miamilite.dtb \
138 zynq-topic-miamiplus.dtb \
139 zynq-zturn-myir.dtb \
[all …]
H A Dzynq-picozed.dts9 #include "zynq-7000.dtsi"
12 model = "Zynq PicoZed Board";
13 compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000";
/OK3568_Linux_fs/buildroot/board/qmtech/zynq/
H A Dreadme.txt2 QMTECH Zynq XC7Z010 Starter Kit
5 This file documents the Buildroot support for the QMTECH [1] Zynq
6 XC7Z010 Starter Kit [2]. It is a low cost (~55$) Zynq based
14 First, configure Buildroot for the QMTECH Zynq board:
34 - zynq-qmtech.dtb
54 Boot the QMTECH Zynq board
69 [2]. QMTECH Zynq XC7Z010 Starter Kit Product Page:
72 [3]. QMTECH Zynq XC7Z010 Starter Kit Hardware User Manual:
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/can/
H A Dxilinx_can.txt1 Xilinx Axi CAN/Zynq CANPS controller Device Tree Bindings
6 - "xlnx,zynq-can-1.0" for Zynq CAN controllers
19 - tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN).
20 - rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in
29 For Zynq CANPS Dts file:
31 compatible = "xlnx,zynq-can-1.0";
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dzynq-7000.dtsi9 compatible = "xlnx,zynq-7000";
103 compatible = "xlnx,zynq-xadc-1.00.a";
111 compatible = "xlnx,zynq-can-1.0";
123 compatible = "xlnx,zynq-can-1.0";
135 compatible = "xlnx,zynq-gpio-1.0";
187 compatible = "xlnx,zynq-ddrc-a05";
210 compatible = "xlnx,zynq-spi-r1p6";
222 compatible = "xlnx,zynq-spi-r1p6";
234 compatible = "cdns,zynq-gem", "cdns,gem";
245 compatible = "cdns,zynq-gem", "cdns,gem";
[all …]
H A Dzynq-zturn.dts6 * Based on zynq-zed.dts which is:
13 /include/ "zynq-7000.dtsi"
16 model = "Zynq Z-Turn MYIR Board";
17 compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
/OK3568_Linux_fs/u-boot/arch/arm/mach-zynq/
H A DKconfig4 default "arch/arm/mach-zynq/u-boot-spl.lds"
31 bool "Zynq DDRC initialization"
39 default "zynq"
46 default "zynq"
50 default "zynq-common"
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/
H A Dxilinx-xadc.txt7 available on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
14 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
20 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
76 compatible = "xlnx,zynq-xadc-1.00.a";
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt1 Device Tree Clock bindings for the Zynq 7000 EPP
3 The Zynq EPP has several different clk providers, each with there own bindings.
7 See Chapter 25 of Zynq TRM for more information about Zynq clocks.
10 The clock controller is a logical abstraction of Zynq's clock tree. It reads
19 (usually 33 MHz oscillators are used for Zynq platforms)
/OK3568_Linux_fs/buildroot/board/zynq/
H A Dreadme.txt1 This is the Buildroot support for Zynq boards. Zynq boards are available from
9 Steps to create a working system for a Zynq board:
35 The DTB for MicroZed is the same as the one for the Zedboard (zynq-zed.dtb),
66 board/xilinx/zynq/ directory of U-Boot for natively supported ps7_init
80 output/build/uboot-xilinx-<pkg version>/board/xilinx/zynq/custom_hw_platform/
/OK3568_Linux_fs/buildroot/board/qmtech/zynq/patches/linux/
H A D0001-DTS-for-QMTech-Zynq-starter-kit.patch4 Subject: [PATCH] DTS for QMTech Zynq starter kit
9 arch/arm/boot/dts/zynq-qmtech.dts | 397 ++++++++++++++++++++++++++++++
11 create mode 100644 arch/arm/boot/dts/zynq-qmtech.dts
13 diff --git a/arch/arm/boot/dts/zynq-qmtech.dts b/arch/arm/boot/dts/zynq-qmtech.dts
17 +++ b/arch/arm/boot/dts/zynq-qmtech.dts
27 + * https://github.com/Xilinx/linux-xlnx/blob/xilinx-v2019.2.01/arch/arm/boot/dts/zynq-zc702.dts
31 +#include "zynq-7000.dtsi"
35 + compatible = "xlnx,zynq-qmtech", "xlnx,zynq-zc702", "xlnx,zynq-7000";
/OK3568_Linux_fs/kernel/arch/arm/mach-zynq/
H A Dcommon.c15 #include <linux/clk/zynq.h>
59 .name = "cpuidle-zynq",
63 * zynq_get_revision - Get Zynq silicon revision
73 np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0"); in zynq_get_revision()
117 soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq"); in zynq_init_machine()
184 "xlnx,zynq-7000",
188 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
/OK3568_Linux_fs/u-boot/include/configs/
H A Dzynq_zc70x.h4 * Configuration settings for the Xilinx Zynq ZC702 and ZC706 boards
5 * See zynq-common.h for Zynq common configs
16 #include <configs/zynq-common.h>
H A Dzynq_zybo.h5 * Configuration for Zynq Development Board - ZYBO
6 * See zynq-common.h for Zynq common configs
22 #include <configs/zynq-common.h>
/OK3568_Linux_fs/u-boot/configs/
H A Dtopic_miamiplus_defconfig6 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamiplus/ps7_regs.txt"
7 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamiplus"
13 CONFIG_SYS_PROMPT="zynq-uboot> "
H A Dtopic_miami_defconfig6 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miami/ps7_regs.txt"
7 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miami"
13 CONFIG_SYS_PROMPT="zynq-uboot> "
H A Dtopic_miamilite_defconfig6 CONFIG_BOOT_INIT_FILE="board/topic/zynq/zynq-topic-miamilite/ps7_regs.txt"
7 CONFIG_DEFAULT_DEVICE_TREE="zynq-topic-miamilite"
13 CONFIG_SYS_PROMPT="zynq-uboot> "
/OK3568_Linux_fs/u-boot/drivers/gpio/
H A Dzynq_gpio.c2 * Xilinx Zynq GPIO device driver
6 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
47 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
50 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
53 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
56 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
59 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
62 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
105 * struct zynq_platform_data - zynq gpio platform data structure
331 { .compatible = "xlnx,zynq-gpio-1.0",
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dsynopsys.txt6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
23 compatible = "xlnx,zynq-ddrc-a05";

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