1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Avnet PicoZed board DTS 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2015 Xilinx, Inc. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun#include "zynq-7000.dtsi" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun/ { 12*4882a593Smuzhiyun model = "Zynq PicoZed Board"; 13*4882a593Smuzhiyun compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000"; 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun aliases { 16*4882a593Smuzhiyun serial0 = &uart1; 17*4882a593Smuzhiyun spi0 = &qspi; 18*4882a593Smuzhiyun mmc0 = &sdhci1; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun memory@0 { 22*4882a593Smuzhiyun device_type = "memory"; 23*4882a593Smuzhiyun reg = <0 0x40000000>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun}; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&uart1 { 28*4882a593Smuzhiyun u-boot,dm-pre-reloc; 29*4882a593Smuzhiyun status = "okay"; 30*4882a593Smuzhiyun}; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun&qspi { 33*4882a593Smuzhiyun u-boot,dm-pre-reloc; 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&sdhci1 { 38*4882a593Smuzhiyun u-boot,dm-pre-reloc; 39*4882a593Smuzhiyun status = "okay"; 40*4882a593Smuzhiyun}; 41