1*4882a593SmuzhiyunXilinx Axi CAN/Zynq CANPS controller Device Tree Bindings 2*4882a593Smuzhiyun--------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : Should be: 6*4882a593Smuzhiyun - "xlnx,zynq-can-1.0" for Zynq CAN controllers 7*4882a593Smuzhiyun - "xlnx,axi-can-1.00.a" for Axi CAN controllers 8*4882a593Smuzhiyun - "xlnx,canfd-1.0" for CAN FD controllers 9*4882a593Smuzhiyun - "xlnx,canfd-2.0" for CAN FD 2.0 controllers 10*4882a593Smuzhiyun- reg : Physical base address and size of the controller 11*4882a593Smuzhiyun registers map. 12*4882a593Smuzhiyun- interrupts : Property with a value describing the interrupt 13*4882a593Smuzhiyun number. 14*4882a593Smuzhiyun- clock-names : List of input clock names 15*4882a593Smuzhiyun - "can_clk", "pclk" (For CANPS), 16*4882a593Smuzhiyun - "can_clk", "s_axi_aclk" (For AXI CAN and CAN FD). 17*4882a593Smuzhiyun (See clock bindings for details). 18*4882a593Smuzhiyun- clocks : Clock phandles (see clock bindings for details). 19*4882a593Smuzhiyun- tx-fifo-depth : Can Tx fifo depth (Zynq, Axi CAN). 20*4882a593Smuzhiyun- rx-fifo-depth : Can Rx fifo depth (Zynq, Axi CAN, CAN FD in 21*4882a593Smuzhiyun sequential Rx mode). 22*4882a593Smuzhiyun- tx-mailbox-count : Can Tx mailbox buffer count (CAN FD). 23*4882a593Smuzhiyun- rx-mailbox-count : Can Rx mailbox buffer count (CAN FD in mailbox Rx 24*4882a593Smuzhiyun mode). 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample: 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunFor Zynq CANPS Dts file: 30*4882a593Smuzhiyun zynq_can_0: can@e0008000 { 31*4882a593Smuzhiyun compatible = "xlnx,zynq-can-1.0"; 32*4882a593Smuzhiyun clocks = <&clkc 19>, <&clkc 36>; 33*4882a593Smuzhiyun clock-names = "can_clk", "pclk"; 34*4882a593Smuzhiyun reg = <0xe0008000 0x1000>; 35*4882a593Smuzhiyun interrupts = <0 28 4>; 36*4882a593Smuzhiyun interrupt-parent = <&intc>; 37*4882a593Smuzhiyun tx-fifo-depth = <0x40>; 38*4882a593Smuzhiyun rx-fifo-depth = <0x40>; 39*4882a593Smuzhiyun }; 40*4882a593SmuzhiyunFor Axi CAN Dts file: 41*4882a593Smuzhiyun axi_can_0: axi-can@40000000 { 42*4882a593Smuzhiyun compatible = "xlnx,axi-can-1.00.a"; 43*4882a593Smuzhiyun clocks = <&clkc 0>, <&clkc 1>; 44*4882a593Smuzhiyun clock-names = "can_clk","s_axi_aclk" ; 45*4882a593Smuzhiyun reg = <0x40000000 0x10000>; 46*4882a593Smuzhiyun interrupt-parent = <&intc>; 47*4882a593Smuzhiyun interrupts = <0 59 1>; 48*4882a593Smuzhiyun tx-fifo-depth = <0x40>; 49*4882a593Smuzhiyun rx-fifo-depth = <0x40>; 50*4882a593Smuzhiyun }; 51*4882a593SmuzhiyunFor CAN FD Dts file: 52*4882a593Smuzhiyun canfd_0: canfd@40000000 { 53*4882a593Smuzhiyun compatible = "xlnx,canfd-1.0"; 54*4882a593Smuzhiyun clocks = <&clkc 0>, <&clkc 1>; 55*4882a593Smuzhiyun clock-names = "can_clk", "s_axi_aclk"; 56*4882a593Smuzhiyun reg = <0x40000000 0x2000>; 57*4882a593Smuzhiyun interrupt-parent = <&intc>; 58*4882a593Smuzhiyun interrupts = <0 59 1>; 59*4882a593Smuzhiyun tx-mailbox-count = <0x20>; 60*4882a593Smuzhiyun rx-fifo-depth = <0x20>; 61*4882a593Smuzhiyun }; 62