xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/xilinx-xadc.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunXilinx XADC device driver
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis binding document describes the bindings for both of them since the
4*4882a593Smuzhiyunbindings are very similar. The Xilinx XADC is a ADC that can be found in the
5*4882a593Smuzhiyunseries 7 FPGAs from Xilinx. The XADC has a DRP interface for communication.
6*4882a593SmuzhiyunCurrently two different frontends for the DRP interface exist. One that is only
7*4882a593Smuzhiyunavailable on the ZYNQ family as a hardmacro in the SoC portion of the ZYNQ. The
8*4882a593Smuzhiyunother one is available on all series 7 platforms and is a softmacro with a AXI
9*4882a593Smuzhiyuninterface. This binding document describes the bindings for both of them since
10*4882a593Smuzhiyunthe bindings are very similar.
11*4882a593Smuzhiyun
12*4882a593SmuzhiyunRequired properties:
13*4882a593Smuzhiyun	- compatible: Should be one of
14*4882a593Smuzhiyun		* "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
15*4882a593Smuzhiyun		  configuration interface to interface to the XADC hardmacro.
16*4882a593Smuzhiyun		* "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
17*4882a593Smuzhiyun		  interface to the XADC hardmacro.
18*4882a593Smuzhiyun	- reg: Address and length of the register set for the device
19*4882a593Smuzhiyun	- interrupts: Interrupt for the XADC control interface.
20*4882a593Smuzhiyun	- clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
21*4882a593Smuzhiyun	  when using the AXI-XADC pcore this must be the clock that provides the
22*4882a593Smuzhiyun	  clock to the AXI bus interface of the core.
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunOptional properties:
25*4882a593Smuzhiyun	- xlnx,external-mux:
26*4882a593Smuzhiyun		* "none": No external multiplexer is used, this is the default
27*4882a593Smuzhiyun		  if the property is omitted.
28*4882a593Smuzhiyun		* "single": External multiplexer mode is used with one
29*4882a593Smuzhiyun		   multiplexer.
30*4882a593Smuzhiyun		* "dual": External multiplexer mode is used with two
31*4882a593Smuzhiyun		  multiplexers for simultaneous sampling.
32*4882a593Smuzhiyun	- xlnx,external-mux-channel: Configures which pair of pins is used to
33*4882a593Smuzhiyun	  sample data in external mux mode.
34*4882a593Smuzhiyun	  Valid values for single external multiplexer mode are:
35*4882a593Smuzhiyun		0: VP/VN
36*4882a593Smuzhiyun		1: VAUXP[0]/VAUXN[0]
37*4882a593Smuzhiyun		2: VAUXP[1]/VAUXN[1]
38*4882a593Smuzhiyun		...
39*4882a593Smuzhiyun		16: VAUXP[15]/VAUXN[15]
40*4882a593Smuzhiyun	  Valid values for dual external multiplexer mode are:
41*4882a593Smuzhiyun		1: VAUXP[0]/VAUXN[0] - VAUXP[8]/VAUXN[8]
42*4882a593Smuzhiyun		2: VAUXP[1]/VAUXN[1] - VAUXP[9]/VAUXN[9]
43*4882a593Smuzhiyun		...
44*4882a593Smuzhiyun		8: VAUXP[7]/VAUXN[7] - VAUXP[15]/VAUXN[15]
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun	  This property needs to be present if the device is configured for
47*4882a593Smuzhiyun	  external multiplexer mode (either single or dual). If the device is
48*4882a593Smuzhiyun	  not using external multiplexer mode the property is ignored.
49*4882a593Smuzhiyun	- xnlx,channels: List of external channels that are connected to the ADC
50*4882a593Smuzhiyun	  Required properties:
51*4882a593Smuzhiyun		* #address-cells: Should be 1.
52*4882a593Smuzhiyun		* #size-cells: Should be 0.
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	  The child nodes of this node represent the external channels which are
55*4882a593Smuzhiyun	  connected to the ADC. If the property is no present no external
56*4882a593Smuzhiyun	  channels will be assumed to be connected.
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun	  Each child node represents one channel and has the following
59*4882a593Smuzhiyun	  properties:
60*4882a593Smuzhiyun		Required properties:
61*4882a593Smuzhiyun			* reg: Pair of pins the channel is connected to.
62*4882a593Smuzhiyun				0: VP/VN
63*4882a593Smuzhiyun				1: VAUXP[0]/VAUXN[0]
64*4882a593Smuzhiyun				2: VAUXP[1]/VAUXN[1]
65*4882a593Smuzhiyun				...
66*4882a593Smuzhiyun				16: VAUXP[15]/VAUXN[15]
67*4882a593Smuzhiyun			  Note each channel number should only be used at most
68*4882a593Smuzhiyun			  once.
69*4882a593Smuzhiyun		Optional properties:
70*4882a593Smuzhiyun			* xlnx,bipolar: If set the channel is used in bipolar
71*4882a593Smuzhiyun			  mode.
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun
74*4882a593SmuzhiyunExamples:
75*4882a593Smuzhiyun	xadc@f8007100 {
76*4882a593Smuzhiyun		compatible = "xlnx,zynq-xadc-1.00.a";
77*4882a593Smuzhiyun		reg = <0xf8007100 0x20>;
78*4882a593Smuzhiyun		interrupts = <0 7 4>;
79*4882a593Smuzhiyun		interrupt-parent = <&gic>;
80*4882a593Smuzhiyun		clocks = <&pcap_clk>;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun		xlnx,channels {
83*4882a593Smuzhiyun			#address-cells = <1>;
84*4882a593Smuzhiyun			#size-cells = <0>;
85*4882a593Smuzhiyun			channel@0 {
86*4882a593Smuzhiyun				reg = <0>;
87*4882a593Smuzhiyun			};
88*4882a593Smuzhiyun			channel@1 {
89*4882a593Smuzhiyun				reg = <1>;
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun			channel@8 {
92*4882a593Smuzhiyun				reg = <8>;
93*4882a593Smuzhiyun			};
94*4882a593Smuzhiyun		};
95*4882a593Smuzhiyun	};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun	xadc@43200000 {
98*4882a593Smuzhiyun		compatible = "xlnx,axi-xadc-1.00.a";
99*4882a593Smuzhiyun		reg = <0x43200000 0x1000>;
100*4882a593Smuzhiyun		interrupts = <0 53 4>;
101*4882a593Smuzhiyun		interrupt-parent = <&gic>;
102*4882a593Smuzhiyun		clocks = <&fpga1_clk>;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun		xlnx,channels {
105*4882a593Smuzhiyun			#address-cells = <1>;
106*4882a593Smuzhiyun			#size-cells = <0>;
107*4882a593Smuzhiyun			channel@0 {
108*4882a593Smuzhiyun				reg = <0>;
109*4882a593Smuzhiyun				xlnx,bipolar;
110*4882a593Smuzhiyun			};
111*4882a593Smuzhiyun		};
112*4882a593Smuzhiyun	};
113