1*4882a593SmuzhiyunDevice Tree Clock bindings for the Zynq 7000 EPP 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Zynq EPP has several different clk providers, each with there own bindings. 4*4882a593SmuzhiyunThe purpose of this document is to document their usage. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunSee clock_bindings.txt for more information on the generic clock bindings. 7*4882a593SmuzhiyunSee Chapter 25 of Zynq TRM for more information about Zynq clocks. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun== Clock Controller == 10*4882a593SmuzhiyunThe clock controller is a logical abstraction of Zynq's clock tree. It reads 11*4882a593Smuzhiyunrequired input clock frequencies from the devicetree and acts as clock provider 12*4882a593Smuzhiyunfor all clock consumers of PS clocks. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun - #clock-cells : Must be 1 16*4882a593Smuzhiyun - compatible : "xlnx,ps7-clkc" 17*4882a593Smuzhiyun - reg : SLCR offset and size taken via syscon < 0x100 0x100 > 18*4882a593Smuzhiyun - ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ 19*4882a593Smuzhiyun (usually 33 MHz oscillators are used for Zynq platforms) 20*4882a593Smuzhiyun - clock-output-names : List of strings used to name the clock outputs. Shall be 21*4882a593Smuzhiyun a list of the outputs given below. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyun - clocks : as described in the clock bindings 25*4882a593Smuzhiyun - clock-names : as described in the clock bindings 26*4882a593Smuzhiyun - fclk-enable : Bit mask to enable FCLKs statically at boot time. 27*4882a593Smuzhiyun Bit [0..3] correspond to FCLK0..FCLK3. The corresponding 28*4882a593Smuzhiyun FCLK will only be enabled if it is actually running at 29*4882a593Smuzhiyun boot time. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunClock inputs: 32*4882a593SmuzhiyunThe following strings are optional parameters to the 'clock-names' property in 33*4882a593Smuzhiyunorder to provide an optional (E)MIO clock source. 34*4882a593Smuzhiyun - swdt_ext_clk 35*4882a593Smuzhiyun - gem0_emio_clk 36*4882a593Smuzhiyun - gem1_emio_clk 37*4882a593Smuzhiyun - mio_clk_XX # with XX = 00..53 38*4882a593Smuzhiyun... 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunClock outputs: 41*4882a593Smuzhiyun 0: armpll 42*4882a593Smuzhiyun 1: ddrpll 43*4882a593Smuzhiyun 2: iopll 44*4882a593Smuzhiyun 3: cpu_6or4x 45*4882a593Smuzhiyun 4: cpu_3or2x 46*4882a593Smuzhiyun 5: cpu_2x 47*4882a593Smuzhiyun 6: cpu_1x 48*4882a593Smuzhiyun 7: ddr2x 49*4882a593Smuzhiyun 8: ddr3x 50*4882a593Smuzhiyun 9: dci 51*4882a593Smuzhiyun 10: lqspi 52*4882a593Smuzhiyun 11: smc 53*4882a593Smuzhiyun 12: pcap 54*4882a593Smuzhiyun 13: gem0 55*4882a593Smuzhiyun 14: gem1 56*4882a593Smuzhiyun 15: fclk0 57*4882a593Smuzhiyun 16: fclk1 58*4882a593Smuzhiyun 17: fclk2 59*4882a593Smuzhiyun 18: fclk3 60*4882a593Smuzhiyun 19: can0 61*4882a593Smuzhiyun 20: can1 62*4882a593Smuzhiyun 21: sdio0 63*4882a593Smuzhiyun 22: sdio1 64*4882a593Smuzhiyun 23: uart0 65*4882a593Smuzhiyun 24: uart1 66*4882a593Smuzhiyun 25: spi0 67*4882a593Smuzhiyun 26: spi1 68*4882a593Smuzhiyun 27: dma 69*4882a593Smuzhiyun 28: usb0_aper 70*4882a593Smuzhiyun 29: usb1_aper 71*4882a593Smuzhiyun 30: gem0_aper 72*4882a593Smuzhiyun 31: gem1_aper 73*4882a593Smuzhiyun 32: sdio0_aper 74*4882a593Smuzhiyun 33: sdio1_aper 75*4882a593Smuzhiyun 34: spi0_aper 76*4882a593Smuzhiyun 35: spi1_aper 77*4882a593Smuzhiyun 36: can0_aper 78*4882a593Smuzhiyun 37: can1_aper 79*4882a593Smuzhiyun 38: i2c0_aper 80*4882a593Smuzhiyun 39: i2c1_aper 81*4882a593Smuzhiyun 40: uart0_aper 82*4882a593Smuzhiyun 41: uart1_aper 83*4882a593Smuzhiyun 42: gpio_aper 84*4882a593Smuzhiyun 43: lqspi_aper 85*4882a593Smuzhiyun 44: smc_aper 86*4882a593Smuzhiyun 45: swdt 87*4882a593Smuzhiyun 46: dbg_trc 88*4882a593Smuzhiyun 47: dbg_apb 89*4882a593Smuzhiyun 90*4882a593SmuzhiyunExample: 91*4882a593Smuzhiyun clkc: clkc@100 { 92*4882a593Smuzhiyun #clock-cells = <1>; 93*4882a593Smuzhiyun compatible = "xlnx,ps7-clkc"; 94*4882a593Smuzhiyun ps-clk-frequency = <33333333>; 95*4882a593Smuzhiyun reg = <0x100 0x100>; 96*4882a593Smuzhiyun clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 97*4882a593Smuzhiyun "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 98*4882a593Smuzhiyun "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 99*4882a593Smuzhiyun "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 100*4882a593Smuzhiyun "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 101*4882a593Smuzhiyun "dma", "usb0_aper", "usb1_aper", "gem0_aper", 102*4882a593Smuzhiyun "gem1_aper", "sdio0_aper", "sdio1_aper", 103*4882a593Smuzhiyun "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 104*4882a593Smuzhiyun "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 105*4882a593Smuzhiyun "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 106*4882a593Smuzhiyun "dbg_trc", "dbg_apb"; 107*4882a593Smuzhiyun # optional props 108*4882a593Smuzhiyun clocks = <&clkc 16>, <&clk_foo>; 109*4882a593Smuzhiyun clock-names = "gem1_emio_clk", "can_mio_clk_23"; 110*4882a593Smuzhiyun }; 111