| /OK3568_Linux_fs/kernel/drivers/clk/tegra/ |
| H A D | clk-pll.c | 276 static void clk_pll_enable_lock(struct tegra_clk_pll *pll) in clk_pll_enable_lock() argument
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
286 val = pll_readl_misc(pll); in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
288 pll_writel_misc(val, pll); in clk_pll_enable_lock()
291 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll) in clk_pll_wait_for_lock() argument
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
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| /OK3568_Linux_fs/kernel/drivers/clk/qcom/ |
| H A D | clk-alpha-pll.c | 12 #include "clk-alpha-pll.h"
142 /* TRION PLL specific settings and offsets */
146 /* LUCID PLL specific settings and offsets */
161 static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, in wait_for_pll() argument
167 const char *name = clk_hw_get_name(&pll->clkr.hw); in wait_for_pll()
169 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
174 ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val); in wait_for_pll()
189 #define wait_for_pll_enable_active(pll) \ argument
190 wait_for_pll(pll, PLL_ACTIVE_FLAG, 0, "enable")
192 #define wait_for_pll_enable_lock(pll) \ argument
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| H A D | clk-pll.c | 17 #include "clk-pll.h"
26 struct clk_pll *pll = to_clk_pll(hw); in clk_pll_enable() local
31 ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val); in clk_pll_enable()
39 /* Disable PLL bypass mode. */ in clk_pll_enable()
40 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL, in clk_pll_enable()
51 /* De-assert active-low PLL reset. */ in clk_pll_enable()
52 ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N, in clk_pll_enable()
57 /* Wait until PLL is locked. */ in clk_pll_enable()
60 /* Enable PLL output. */ in clk_pll_enable()
61 return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL, in clk_pll_enable()
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| /OK3568_Linux_fs/kernel/drivers/clk/mediatek/ |
| H A D | clk-pll.c | 33 * a divider in the PLL feedback loop which consists of 7 bits for the integer
57 struct mtk_clk_pll *pll = to_mtk_clk_pll(hw); in mtk_pll_is_prepared() local
59 return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0; in mtk_pll_is_prepared()
62 static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin, in __mtk_pll_recalc_rate() argument
65 int pcwbits = pll->data->pcwbits; in __mtk_pll_recalc_rate()
71 /* The fractional part of the PLL divider. */ in __mtk_pll_recalc_rate()
72 ibits = pll->data->pcwibits ? pll->data->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
89 static void __mtk_pll_tuner_enable(struct mtk_clk_pll *pll) in __mtk_pll_tuner_enable() argument
93 if (pll->tuner_en_addr) { in __mtk_pll_tuner_enable()
94 r = readl(pll->tuner_en_addr) | BIT(pll->data->tuner_en_bit); in __mtk_pll_tuner_enable()
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| /OK3568_Linux_fs/kernel/drivers/clk/sprd/ |
| H A D | pll.c | 3 // Spreadtrum pll clock driver
13 #include "pll.h"
18 #define pindex(pll, member) \ argument
19 (pll->factors[member].shift / (8 * sizeof(pll->regs_num)))
21 #define pshift(pll, member) \ argument
22 (pll->factors[member].shift % (8 * sizeof(pll->regs_num)))
24 #define pwidth(pll, member) \ argument
25 pll->factors[member].width
27 #define pmask(pll, member) \ argument
28 ((pwidth(pll, member)) ? \
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/dsi/pll/ |
| H A D | dsi_pll.c | 8 static int dsi_pll_enable(struct msm_dsi_pll *pll) in dsi_pll_enable() argument
16 if (unlikely(pll->pll_on)) in dsi_pll_enable()
20 for (i = 0; i < pll->en_seq_cnt; i++) { in dsi_pll_enable()
21 ret = pll->enable_seqs[i](pll); in dsi_pll_enable()
22 DBG("DSI PLL %s after sequence #%d", in dsi_pll_enable()
29 DRM_ERROR("DSI PLL failed to lock\n"); in dsi_pll_enable()
33 pll->pll_on = true; in dsi_pll_enable()
38 static void dsi_pll_disable(struct msm_dsi_pll *pll) in dsi_pll_disable() argument
40 if (unlikely(!pll->pll_on)) in dsi_pll_disable()
43 pll->disable_seq(pll); in dsi_pll_disable()
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| H A D | dsi_pll_14nm.c | 13 * DSI PLL 14nm - clock diagram (eg: DSI0):
155 * also sets the slave DSI PLL's post-dividers if in Dual DSI mode
165 struct dsi_pll_14nm *pll; member
171 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
172 * mode, where the master PLL's clk_ops needs access the slave's private data
209 DBG("DSI PLL is %slocked", pll_locked ? "" : "*not* "); in pll_14nm_poll_for_ready()
214 static void dsi_pll_14nm_input_init(struct dsi_pll_14nm *pll) in dsi_pll_14nm_input_init() argument
216 pll->in.fref = pll->vco_ref_clk_rate; in dsi_pll_14nm_input_init()
217 pll->in.fdata = 0; in dsi_pll_14nm_input_init()
218 pll->in.dsiclk_sel = 1; /* Use the /2 path in Mux */ in dsi_pll_14nm_input_init()
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| H A D | dsi_pll_7nm.c | 14 * DSI PLL 7nm - clock diagram (eg: DSI0): TODO: updated CPHY diagram
127 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
128 * mode, where the master PLL's clk_ops needs access the slave's private data
132 static void dsi_pll_setup_config(struct dsi_pll_7nm *pll) in dsi_pll_setup_config() argument
134 struct dsi_pll_config *config = &pll->pll_configuration; in dsi_pll_setup_config()
136 config->ref_freq = pll->vco_ref_clk_rate; in dsi_pll_setup_config()
156 static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll) in dsi_pll_calc_dec_frac() argument
158 struct dsi_pll_config *config = &pll->pll_configuration; in dsi_pll_calc_dec_frac()
159 struct dsi_pll_regs *regs = &pll->reg_setup; in dsi_pll_calc_dec_frac()
160 u64 fref = pll->vco_ref_clk_rate; in dsi_pll_calc_dec_frac()
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 32 * struct clk_pllv3 - IMX PLL clock version 3
34 * @base: base address of PLL registers
35 * @power_bit: pll power bit mask
36 * @powerup_set: set power_bit to power up the PLL
43 * IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
60 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) in clk_pllv3_wait_lock() argument
62 u32 val = readl_relaxed(pll->base) & pll->power_bit; in clk_pllv3_wait_lock()
64 /* No need to wait for lock when pll is not powered up */ in clk_pllv3_wait_lock()
65 if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) in clk_pllv3_wait_lock()
68 return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK, in clk_pllv3_wait_lock()
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| H A D | clk-pll14xx.c | 90 struct clk_pll14xx *pll, unsigned long rate) in imx_get_pll_settings() argument
92 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in imx_get_pll_settings()
95 for (i = 0; i < pll->rate_count; i++) in imx_get_pll_settings()
105 struct clk_pll14xx *pll = to_clk_pll14xx(hw); in clk_pll14xx_round_rate() local
106 const struct imx_pll14xx_rate_table *rate_table = pll->rate_table; in clk_pll14xx_round_rate()
110 for (i = 0; i < pll->rate_count; i++) in clk_pll14xx_round_rate()
121 struct clk_pll14xx *pll = to_clk_pll14xx(hw); in clk_pll1416x_recalc_rate() local
125 pll_div = readl_relaxed(pll->base + 4); in clk_pll1416x_recalc_rate()
139 struct clk_pll14xx *pll = to_clk_pll14xx(hw); in clk_pll1443x_recalc_rate() local
144 pll_div_ctl0 = readl_relaxed(pll->base + 4); in clk_pll1443x_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/bcm/ |
| H A D | clk-iproc-pll.c | 29 * PLL MACRO_SELECT modes 0 to 5 choose pre-calculated PLL output frequencies
30 * from a look-up table. Mode 7 allows user to manipulate PLL clock dividers
34 /* number of delay loops waiting for PLL to lock */
85 struct iproc_pll *pll; member
128 static int pll_get_rate_index(struct iproc_pll *pll, unsigned int target_rate) in pll_get_rate_index() argument
132 for (i = 0; i < pll->num_vco_entries; i++) in pll_get_rate_index()
133 if (target_rate == pll->vco_param[i].rate) in pll_get_rate_index()
136 if (i >= pll->num_vco_entries) in pll_get_rate_index()
157 static int pll_wait_for_lock(struct iproc_pll *pll) in pll_wait_for_lock() argument
160 const struct iproc_pll_ctrl *ctrl = pll->ctrl; in pll_wait_for_lock()
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| H A D | clk-iproc-armpll.c | 76 static unsigned int __get_fid(struct iproc_arm_pll *pll) in __get_fid() argument
81 val = readl(pll->base + IPROC_CLK_ARM_DIV_OFFSET); in __get_fid()
90 val = readl(pll->base + IPROC_CLK_POLICY_FREQ_OFFSET); in __get_fid()
94 val = readl(pll->base + IPROC_CLK_POLICY_DBG_OFFSET); in __get_fid()
113 * - PLL channel 0 (slow clock)
114 * - PLL channel 1 (fast clock)
116 static int __get_mdiv(struct iproc_arm_pll *pll) in __get_mdiv() argument
122 fid = __get_fid(pll); in __get_mdiv()
131 val = readl(pll->base + IPROC_CLK_PLLARMC_OFFSET); in __get_mdiv()
138 val = readl(pll->base + IPROC_CLK_PLLARMCTL5_OFFSET); in __get_mdiv()
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| /OK3568_Linux_fs/kernel/drivers/clk/rockchip/ |
| H A D | clk-pll.c | 68 static void rockchip_boost_disable_low(struct rockchip_clk_pll *pll);
74 static inline void rockchip_boost_disable_low(struct rockchip_clk_pll *pll) {} in rockchip_boost_disable_low() argument
103 struct rockchip_clk_pll *pll; in rockchip_pll_clk_adaptive_scaling() local
108 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_adaptive_scaling()
109 if (!pll) in rockchip_pll_clk_adaptive_scaling()
112 pll->sel = sel; in rockchip_pll_clk_adaptive_scaling()
122 struct rockchip_clk_pll *pll; in rockchip_pll_clk_rate_to_scale() local
128 pll = to_rockchip_clk_pll(__clk_get_hw(parent)); in rockchip_pll_clk_rate_to_scale()
129 if (!pll) in rockchip_pll_clk_rate_to_scale()
132 rate_table = pll->rate_table; in rockchip_pll_clk_rate_to_scale()
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/aty/ |
| H A D | mach64_ct.c | 18 static int aty_valid_pll_ct (const struct fb_info *info, u32 vclk_per, struct pll_ct *pll);
19 static int aty_dsp_gt (const struct fb_info *info, u32 bpp, struct pll_ct *pll);
20 static int aty_var_to_pll_ct(const struct fb_info *info, u32 vclk_per, u32 bpp, union aty_pll *pll);
21 static u32 aty_pll_to_var_ct(const struct fb_info *info, const union aty_pll *pll);
105 * PLL programming (Mach64 CT family)
120 static int aty_dsp_gt(const struct fb_info *info, u32 bpp, struct pll_ct *pll) in aty_dsp_gt() argument
127 multiplier = ((u32)pll->mclk_fb_div) * pll->vclk_post_div_real; in aty_dsp_gt()
128 divider = ((u32)pll->vclk_fb_div) * pll->xclk_ref_div; in aty_dsp_gt()
130 ras_multiplier = pll->xclkmaxrasdelay; in aty_dsp_gt()
136 vshift = (6 - 2) - pll->xclk_post_div; /* FIFO is 64 bits wide in accelerator mode ... */ in aty_dsp_gt()
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| /OK3568_Linux_fs/kernel/drivers/media/i2c/ |
| H A D | smiapp-pll.c | 3 * drivers/media/i2c/smiapp-pll.c
16 #include "smiapp-pll.h"
53 static void print_pll(struct device *dev, struct smiapp_pll *pll) in print_pll() argument
55 dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div); in print_pll()
56 dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier); in print_pll()
57 if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) { in print_pll()
58 dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div); in print_pll()
59 dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div); in print_pll()
61 dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div); in print_pll()
62 dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div); in print_pll()
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| /OK3568_Linux_fs/kernel/drivers/clk/meson/ |
| H A D | clk-pll.c | 11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
38 #include "clk-pll.h"
46 static int __pll_round_closest_mult(struct meson_clk_pll_data *pll) in __pll_round_closest_mult() argument
48 if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) && in __pll_round_closest_mult()
49 !MESON_PARM_APPLICABLE(&pll->frac)) in __pll_round_closest_mult()
58 struct meson_clk_pll_data *pll) in __pll_params_to_rate() argument
62 if (frac && MESON_PARM_APPLICABLE(&pll->frac)) { in __pll_params_to_rate()
66 (1 << pll->frac.width)); in __pll_params_to_rate()
76 struct meson_clk_pll_data *pll = meson_clk_pll_data(clk); in meson_clk_pll_recalc_rate() local
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| /OK3568_Linux_fs/kernel/drivers/clk/samsung/ |
| H A D | clk-pll.c | 6 * This file contains the utility functions to register the pll clocks.
16 #include "clk-pll.h"
24 /* PLL enable control bit offset in @con_reg register */
26 /* PLL lock status bit offset in @con_reg register */
36 struct samsung_clk_pll *pll, unsigned long rate) in samsung_get_pll_settings() argument
38 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_get_pll_settings()
41 for (i = 0; i < pll->rate_count; i++) { in samsung_get_pll_settings()
52 struct samsung_clk_pll *pll = to_clk_pll(hw); in samsung_pll_round_rate() local
53 const struct samsung_pll_rate_table *rate_table = pll->rate_table; in samsung_pll_round_rate()
57 for (i = 0; i < pll->rate_count; i++) { in samsung_pll_round_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/pistachio/ |
| H A D | clk-pll.c | 65 /* Fractional PLL operating modes */
78 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg) in pll_readl() argument
80 return readl(pll->base + reg); in pll_readl()
83 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg) in pll_writel() argument
85 writel(val, pll->base + reg); in pll_writel()
88 static inline void pll_lock(struct pistachio_clk_pll *pll) in pll_lock() argument
90 while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK)) in pll_lock()
107 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_get_mode() local
110 val = pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_DSMPD; in pll_frac_get_mode()
116 struct pistachio_clk_pll *pll = to_pistachio_pll(hw); in pll_frac_set_mode() local
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| /OK3568_Linux_fs/u-boot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 67 * How to calculate the PLL(from TRM V0.3 Part 1 Page 63):
68 * Formulas also embedded within the Fractional PLL Verilog model:
73 * FOUTVCO = Fractional PLL non-divided output frequency
74 * FOUTPOSTDIV = Fractional PLL divided output frequency
76 * FREF = Fractional PLL input reference frequency, (the OSC_HZ 24MHz input)
77 * REFDIV = Fractional PLL input reference clock divider
229 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings() argument
231 struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
239 if (pll->type == pll_rk3588) in rockchip_get_pll_settings()
248 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, in rk3036_pll_set_rate() argument
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| /OK3568_Linux_fs/kernel/drivers/clk/baikal-t1/ |
| H A D | ccu-pll.c | 9 * Baikal-T1 CCU PLL interface driver
12 #define pr_fmt(fmt) "bt1-ccu-pll: " fmt
29 #include "ccu-pll.h"
88 static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk, in ccu_pll_reset() argument
97 regmap_update_bits(pll->sys_regs, pll->reg_ctl, in ccu_pll_reset()
100 return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val, in ccu_pll_reset()
107 struct ccu_pll *pll = to_ccu_pll(hw); in ccu_pll_enable() local
117 regmap_read(pll->sys_regs, pll->reg_ctl, &val); in ccu_pll_enable()
121 spin_lock_irqsave(&pll->lock, flags); in ccu_pll_enable()
122 regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN); in ccu_pll_enable()
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| /OK3568_Linux_fs/kernel/arch/mips/ath79/ |
| H A D | clock.c | 99 u32 pll; in ar71xx_clocks_init() local
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
107 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1; in ar71xx_clocks_init()
110 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_clocks_init()
113 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_clocks_init()
116 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_clocks_init()
127 u32 pll; in ar724x_clocks_init() local
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
133 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK); in ar724x_clocks_init()
134 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2; in ar724x_clocks_init()
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| /OK3568_Linux_fs/kernel/drivers/clk/x86/ |
| H A D | clk-cgu-pll.c | 41 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_recalc_rate() local
45 spin_lock_irqsave(&pll->lock, flags); in lgm_pll_recalc_rate()
46 mult = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 0, 12); in lgm_pll_recalc_rate()
47 div = lgm_get_clk_val(pll->membase, PLL_REF_DIV(pll->reg), 18, 6); in lgm_pll_recalc_rate()
48 frac = lgm_get_clk_val(pll->membase, pll->reg, 2, 24); in lgm_pll_recalc_rate()
49 spin_unlock_irqrestore(&pll->lock, flags); in lgm_pll_recalc_rate()
51 if (pll->type == TYPE_LJPLL) in lgm_pll_recalc_rate()
59 struct lgm_clk_pll *pll = to_lgm_clk_pll(hw); in lgm_pll_is_enabled() local
63 spin_lock_irqsave(&pll->lock, flags); in lgm_pll_is_enabled()
64 ret = lgm_get_clk_val(pll->membase, pll->reg, 0, 1); in lgm_pll_is_enabled()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/msm/hdmi/ |
| H A D | hdmi_phy_8996.c | 33 /* pll mmio base */
81 static inline struct hdmi_phy *pll_get_phy(struct hdmi_pll_8996 *pll) in pll_get_phy() argument
83 return platform_get_drvdata(pll->pdev); in pll_get_phy()
86 static inline void hdmi_pll_write(struct hdmi_pll_8996 *pll, int offset, in hdmi_pll_write() argument
89 msm_writel(data, pll->mmio_qserdes_com + offset); in hdmi_pll_write()
92 static inline u32 hdmi_pll_read(struct hdmi_pll_8996 *pll, int offset) in hdmi_pll_read() argument
94 return msm_readl(pll->mmio_qserdes_com + offset); in hdmi_pll_read()
97 static inline void hdmi_tx_chan_write(struct hdmi_pll_8996 *pll, int channel, in hdmi_tx_chan_write() argument
100 msm_writel(data, pll->mmio_qserdes_tx[channel] + offset); in hdmi_tx_chan_write()
398 struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); in hdmi_8996_pll_set_clk_rate() local
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-keystone/ |
| H A D | clock.c | 2 * Keystone2: pll initialization
47 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
69 if (data->pll == MAIN_PLL) in configure_mult_div()
70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
78 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
83 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, in configure_mult_div()
87 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
101 tmp = pllctl_reg_read(data->pll, secctl); in configure_main_pll()
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| /OK3568_Linux_fs/kernel/drivers/clk/st/ |
| H A D | clkgen-pll.c | 24 * PLL configuration register bits for PLL3200 C32
35 * PLL configuration register bits for PLL4600 C28
124 * DOC: Clock Generated by PLL, rate set and enabled by bootloader
134 * PLL clock that is integrated in the ClockGenA instances on the STiH415
138 * @type: PLL instance type.
139 * @regs_base: base of the PLL configuration register(s).
168 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_locked() local
169 u32 locked = CLKGEN_READ(pll, locked_status); in clkgen_pll_is_locked()
176 struct clkgen_pll *pll = to_clkgen_pll(hw); in clkgen_pll_is_enabled() local
177 u32 poweroff = CLKGEN_READ(pll, pdn_status); in clkgen_pll_is_enabled()
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