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/OK3568_Linux_fs/u-boot/arch/arm/mach-imx/
H A Dcache.c9 #include <asm/pl310.h>
42 struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE; in v7_outer_cache_enable() local
51 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
55 * is cleared, PL310 treats Normal Shared Non-cacheable in v7_outer_cache_enable()
58 setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE); in v7_outer_cache_enable()
69 writel(0x132, &pl310->pl310_tag_latency_ctrl); in v7_outer_cache_enable()
70 writel(0x132, &pl310->pl310_data_latency_ctrl); in v7_outer_cache_enable()
72 val = readl(&pl310->pl310_prefetch_ctrl); in v7_outer_cache_enable()
78 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0 in v7_outer_cache_enable()
79 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2 in v7_outer_cache_enable()
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/lib/
H A Dcache-pl310.c11 #include <asm/pl310.h>
15 struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; variable
19 writel(0, &pl310->pl310_cache_sync); in pl310_cache_sync()
26 assoc_16 = readl(&pl310->pl310_aux_ctrl) & in pl310_background_op_all_ways()
44 pl310_background_op_all_ways(&pl310->pl310_inv_way); in v7_outer_cache_inval_all()
49 pl310_background_op_all_ways(&pl310->pl310_clean_inv_way); in v7_outer_cache_flush_all()
55 /* PL310 currently supports only 32 bytes cache line */ in v7_outer_cache_flush_range()
60 * the first 5 bits are 0 as required by PL310 TRM in v7_outer_cache_flush_range()
65 writel(pa, &pl310->pl310_clean_inv_line_pa); in v7_outer_cache_flush_range()
73 /* PL310 currently supports only 32 bytes cache line */ in v7_outer_cache_inval_range()
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/arm/
H A Dl2c2x0.yaml14 PL220/PL310 and variants) based level 2 cache controller. All these various
34 - arm,pl310-cache
37 # DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
38 - bcm,bcm11351-a2-pl310-cache
42 - brcm,bcm11351-a2-pl310-cache
53 # with arm,pl310-cache controller.
55 - const: arm,pl310-cache
109 I/O coherent mode. Valid only when the arm,pl310-cache compatible
157 description: The default behavior of the L220 or PL310 cache
166 description: enable parity checking on the L2 cache (L220 or PL310).
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/OK3568_Linux_fs/u-boot/arch/arm/mach-socfpga/
H A Dmisc.c22 #include <asm/pl310.h>
26 static const struct pl310_regs *const pl310 = variable
59 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
62 setbits_le32(&pl310->pl310_aux_ctrl, in v7_outer_cache_enable()
68 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
74 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_disable()
H A Dmisc_arria10.c22 #include <asm/pl310.h>
34 static struct pl310_regs *const pl310 = variable
92 writel(0x1, &pl310->pl310_addr_filter_start); in arch_early_init_r()
H A Dspl.c9 #include <asm/pl310.h>
32 static struct pl310_regs *const pl310 = variable
120 writel(0x1, &pl310->pl310_addr_filter_start); in board_init_f()
H A Dmisc_gen5.c23 #include <asm/pl310.h>
29 static struct pl310_regs *const pl310 = variable
276 writel(0x1, &pl310->pl310_addr_filter_start); in arch_early_init_r()
/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dvexpress-v2p-ca9.dts165 compatible = "arm,pl310-cache";
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
234 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
277 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
291 /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
H A Dartpec6.dtsi61 next-level-cache = <&pl310>;
68 next-level-cache = <&pl310>;
133 pl310: cache-controller@faf10000 { label
134 compatible = "arm,pl310-cache";
H A Dvf610.dtsi14 compatible = "arm,pl310-cache";
/OK3568_Linux_fs/kernel/arch/arm/mm/
H A DKconfig980 or PL310 cache controller, but where its use is optional.
1003 of the L220 and PL310 outer cache controllers.
1008 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1010 The PL310 L2 cache controller implements three types of Clean &
1016 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1020 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1022 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1024 PL310 can handle normal accesses while it is in progress. Under very
1026 PL310 treats a cacheable write transaction during a Clean &
1031 bool "PL310 errata: cache sync operation may be faulty"
[all …]
H A Dcache-l2x0.c439 * 588369: PL310 R0P0->R1P0, fixed R2P0.
447 * 727915: PL310 R2P0->R3P0, fixed R3P1.
453 * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
458 * 753970: PL310 R3P0, fixed R3P1.
463 * 769419: PL310 R0P0->R3P1, fixed R3P2.
574 /* restore pl310 setup */ in l2c310_configure()
1325 * coherent, and potentially harmful in certain situations (PCIe/PL310
1751 L2C_ID("arm,pl310-cache", of_l2c310_data),
1752 L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
1757 L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
[all …]
H A Dcache-tauros3.h15 * Marvell Tauros3 L2CC is compatible with PL310 r0p0
/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/
H A Dcpu.c11 #include <asm/pl310.h>
369 struct pl310_regs *const pl310 = in arch_cpu_init() local
397 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in arch_cpu_init()
560 struct pl310_regs *const pl310 = in v7_outer_cache_enable() local
577 setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
583 struct pl310_regs *const pl310 = in v7_outer_cache_disable() local
586 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_disable()
/OK3568_Linux_fs/kernel/arch/arm/mach-imx/
H A Dpm-imx6.c155 .pl310_compat = "arm,pl310-cache",
165 .pl310_compat = "arm,pl310-cache",
175 .pl310_compat = "arm,pl310-cache",
185 .pl310_compat = "arm,pl310-cache",
195 .pl310_compat = "arm,pl310-cache",
551 pr_warn("%s: failed to get pl310-cache base %d!\n", in imx6q_suspend_init()
/OK3568_Linux_fs/kernel/drivers/soc/tegra/
H A DKconfig22 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
36 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
/OK3568_Linux_fs/kernel/arch/arm/mach-mvebu/
H A Dcoherency.c180 * We should switch the PL310 to I/O coherency mode only if in armada_375_380_coherency_init()
187 * Add the PL310 property "arm,io-coherent". This makes sure the in armada_375_380_coherency_init()
193 for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") { in armada_375_380_coherency_init()
/OK3568_Linux_fs/kernel/arch/arm/mach-ux500/
H A Dcpu-db8500.c38 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache"); in ux500_l2x0_unlock()
48 * already enabled, so we do it right here instead. The PL310 has in ux500_l2x0_unlock()
/OK3568_Linux_fs/kernel/arch/arm/mach-tango/
H A DKconfig5 # Cortex-A9 MPCore r3p0, PL310 r3p2
/OK3568_Linux_fs/kernel/arch/arm/mach-socfpga/
H A DKconfig20 select PL310_ERRATA_753970 if PL310
/OK3568_Linux_fs/kernel/arch/arm/mach-highbank/
H A Dsmc.S11 * used to modify the PL310 secure registers.
/OK3568_Linux_fs/kernel/arch/arm/mach-berlin/
H A Dberlin.c27 * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
/OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/
H A Dcache.c30 * Systems with an architectural L2 cache must not use the PL310. in config_cache()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Dst,sti-irq-syscfg.txt5 and PL310 L2 Cache IRQs are controlled using System Configuration registers.
/OK3568_Linux_fs/kernel/arch/arm/mach-omap2/
H A Domap-smc.S16 * used to modify the PL310 secure registers.

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