1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2010
3*4882a593Smuzhiyun * Texas Instruments, <www.ti.com>
4*4882a593Smuzhiyun * Aneesh V <aneesh@ti.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #include <linux/types.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/armv7.h>
11*4882a593Smuzhiyun #include <asm/pl310.h>
12*4882a593Smuzhiyun #include <config.h>
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
16*4882a593Smuzhiyun
pl310_cache_sync(void)17*4882a593Smuzhiyun static void pl310_cache_sync(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun writel(0, &pl310->pl310_cache_sync);
20*4882a593Smuzhiyun }
21*4882a593Smuzhiyun
pl310_background_op_all_ways(u32 * op_reg)22*4882a593Smuzhiyun static void pl310_background_op_all_ways(u32 *op_reg)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun u32 assoc_16, associativity, way_mask;
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun assoc_16 = readl(&pl310->pl310_aux_ctrl) &
27*4882a593Smuzhiyun PL310_AUX_CTRL_ASSOCIATIVITY_MASK;
28*4882a593Smuzhiyun if (assoc_16)
29*4882a593Smuzhiyun associativity = 16;
30*4882a593Smuzhiyun else
31*4882a593Smuzhiyun associativity = 8;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun way_mask = (1 << associativity) - 1;
34*4882a593Smuzhiyun /* Invalidate all ways */
35*4882a593Smuzhiyun writel(way_mask, op_reg);
36*4882a593Smuzhiyun /* Wait for all ways to be invalidated */
37*4882a593Smuzhiyun while (readl(op_reg) && way_mask)
38*4882a593Smuzhiyun ;
39*4882a593Smuzhiyun pl310_cache_sync();
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
v7_outer_cache_inval_all(void)42*4882a593Smuzhiyun void v7_outer_cache_inval_all(void)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun pl310_background_op_all_ways(&pl310->pl310_inv_way);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
v7_outer_cache_flush_all(void)47*4882a593Smuzhiyun void v7_outer_cache_flush_all(void)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun pl310_background_op_all_ways(&pl310->pl310_clean_inv_way);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun /* Flush(clean invalidate) memory from start to stop-1 */
v7_outer_cache_flush_range(u32 start,u32 stop)53*4882a593Smuzhiyun void v7_outer_cache_flush_range(u32 start, u32 stop)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun /* PL310 currently supports only 32 bytes cache line */
56*4882a593Smuzhiyun u32 pa, line_size = 32;
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * Align to the beginning of cache-line - this ensures that
60*4882a593Smuzhiyun * the first 5 bits are 0 as required by PL310 TRM
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun start &= ~(line_size - 1);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun for (pa = start; pa < stop; pa = pa + line_size)
65*4882a593Smuzhiyun writel(pa, &pl310->pl310_clean_inv_line_pa);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun pl310_cache_sync();
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* invalidate memory from start to stop-1 */
v7_outer_cache_inval_range(u32 start,u32 stop)71*4882a593Smuzhiyun void v7_outer_cache_inval_range(u32 start, u32 stop)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun /* PL310 currently supports only 32 bytes cache line */
74*4882a593Smuzhiyun u32 pa, line_size = 32;
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * If start address is not aligned to cache-line do not
78*4882a593Smuzhiyun * invalidate the first cache-line
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun if (start & (line_size - 1)) {
81*4882a593Smuzhiyun printf("ERROR: %s - start address is not aligned - 0x%08x\n",
82*4882a593Smuzhiyun __func__, start);
83*4882a593Smuzhiyun /* move to next cache line */
84*4882a593Smuzhiyun start = (start + line_size - 1) & ~(line_size - 1);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /*
88*4882a593Smuzhiyun * If stop address is not aligned to cache-line do not
89*4882a593Smuzhiyun * invalidate the last cache-line
90*4882a593Smuzhiyun */
91*4882a593Smuzhiyun if (stop & (line_size - 1)) {
92*4882a593Smuzhiyun printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
93*4882a593Smuzhiyun __func__, stop);
94*4882a593Smuzhiyun /* align to the beginning of this cache line */
95*4882a593Smuzhiyun stop &= ~(line_size - 1);
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun for (pa = start; pa < stop; pa = pa + line_size)
99*4882a593Smuzhiyun writel(pa, &pl310->pl310_inv_line_pa);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun pl310_cache_sync();
102*4882a593Smuzhiyun }
103