1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Marvell Tauros3 cache controller includes 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * based on GPL'ed 2.6 kernel sources 8*4882a593Smuzhiyun * (c) Marvell International Ltd. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __ASM_ARM_HARDWARE_TAUROS3_H 12*4882a593Smuzhiyun #define __ASM_ARM_HARDWARE_TAUROS3_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * Marvell Tauros3 L2CC is compatible with PL310 r0p0 16*4882a593Smuzhiyun * but with PREFETCH_CTRL (r2p0) and an additional event counter. 17*4882a593Smuzhiyun * Also, there is AUX2_CTRL for some Marvell specific control. 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define TAUROS3_EVENT_CNT2_CFG 0x224 21*4882a593Smuzhiyun #define TAUROS3_EVENT_CNT2_VAL 0x228 22*4882a593Smuzhiyun #define TAUROS3_INV_ALL 0x780 23*4882a593Smuzhiyun #define TAUROS3_CLEAN_ALL 0x784 24*4882a593Smuzhiyun #define TAUROS3_AUX2_CTRL 0x820 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Registers shifts and masks */ 27*4882a593Smuzhiyun #define TAUROS3_AUX2_CTRL_LINEFILL_BURST8_EN (1 << 2) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif 30