1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2015 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/armv7.h>
9*4882a593Smuzhiyun #include <asm/pl310.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/mach-imx/sys_proto.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifndef CONFIG_SYS_DCACHE_OFF
enable_caches(void)14*4882a593Smuzhiyun void enable_caches(void)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
17*4882a593Smuzhiyun enum dcache_option option = DCACHE_WRITETHROUGH;
18*4882a593Smuzhiyun #else
19*4882a593Smuzhiyun enum dcache_option option = DCACHE_WRITEBACK;
20*4882a593Smuzhiyun #endif
21*4882a593Smuzhiyun /* Avoid random hang when download by usb */
22*4882a593Smuzhiyun invalidate_dcache_all();
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* Enable D-cache. I-cache is already enabled in start.S */
25*4882a593Smuzhiyun dcache_enable();
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Enable caching on OCRAM and ROM */
28*4882a593Smuzhiyun mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
29*4882a593Smuzhiyun ROMCP_ARB_END_ADDR,
30*4882a593Smuzhiyun option);
31*4882a593Smuzhiyun mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
32*4882a593Smuzhiyun IRAM_SIZE,
33*4882a593Smuzhiyun option);
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun #endif
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #ifndef CONFIG_SYS_L2CACHE_OFF
38*4882a593Smuzhiyun #ifdef CONFIG_SYS_L2_PL310
39*4882a593Smuzhiyun #define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
v7_outer_cache_enable(void)40*4882a593Smuzhiyun void v7_outer_cache_enable(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
43*4882a593Smuzhiyun struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
44*4882a593Smuzhiyun unsigned int val;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * Must disable the L2 before changing the latency parameters
49*4882a593Smuzhiyun * and auxiliary control register.
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Set bit 22 in the auxiliary control register. If this bit
55*4882a593Smuzhiyun * is cleared, PL310 treats Normal Shared Non-cacheable
56*4882a593Smuzhiyun * accesses as Cacheable no-allocate.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun if (is_mx6sl() || is_mx6sll()) {
61*4882a593Smuzhiyun val = readl(&iomux->gpr[11]);
62*4882a593Smuzhiyun if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
63*4882a593Smuzhiyun /* L2 cache configured as OCRAM, reset it */
64*4882a593Smuzhiyun val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
65*4882a593Smuzhiyun writel(val, &iomux->gpr[11]);
66*4882a593Smuzhiyun }
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun writel(0x132, &pl310->pl310_tag_latency_ctrl);
70*4882a593Smuzhiyun writel(0x132, &pl310->pl310_data_latency_ctrl);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun val = readl(&pl310->pl310_prefetch_ctrl);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Turn on the L2 I/D prefetch */
75*4882a593Smuzhiyun val |= 0x30000000;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /*
78*4882a593Smuzhiyun * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
79*4882a593Smuzhiyun * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
80*4882a593Smuzhiyun * But according to ARM PL310 errata: 752271
81*4882a593Smuzhiyun * ID: 752271: Double linefill feature can cause data corruption
82*4882a593Smuzhiyun * Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
83*4882a593Smuzhiyun * Workaround: The only workaround to this erratum is to disable the
84*4882a593Smuzhiyun * double linefill feature. This is the default behavior.
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #ifndef CONFIG_MX6Q
88*4882a593Smuzhiyun val |= 0x40800000;
89*4882a593Smuzhiyun #endif
90*4882a593Smuzhiyun writel(val, &pl310->pl310_prefetch_ctrl);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun val = readl(&pl310->pl310_power_ctrl);
93*4882a593Smuzhiyun val |= L2X0_DYNAMIC_CLK_GATING_EN;
94*4882a593Smuzhiyun val |= L2X0_STNDBY_MODE_EN;
95*4882a593Smuzhiyun writel(val, &pl310->pl310_power_ctrl);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
v7_outer_cache_disable(void)100*4882a593Smuzhiyun void v7_outer_cache_disable(void)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun #endif /* !CONFIG_SYS_L2_PL310 */
107*4882a593Smuzhiyun #endif /* !CONFIG_SYS_L2CACHE_OFF */
108