xref: /OK3568_Linux_fs/kernel/drivers/soc/tegra/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyunif ARCH_TEGRA
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun# 32-bit ARM SoCs
5*4882a593Smuzhiyunif ARM
6*4882a593Smuzhiyun
7*4882a593Smuzhiyunconfig ARCH_TEGRA_2x_SOC
8*4882a593Smuzhiyun	bool "Enable support for Tegra20 family"
9*4882a593Smuzhiyun	select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
10*4882a593Smuzhiyun	select ARM_ERRATA_720789
11*4882a593Smuzhiyun	select ARM_ERRATA_754327 if SMP
12*4882a593Smuzhiyun	select ARM_ERRATA_764369 if SMP
13*4882a593Smuzhiyun	select PINCTRL_TEGRA20
14*4882a593Smuzhiyun	select PL310_ERRATA_727915 if CACHE_L2X0
15*4882a593Smuzhiyun	select PL310_ERRATA_769419 if CACHE_L2X0
16*4882a593Smuzhiyun	select SOC_TEGRA_FLOWCTRL
17*4882a593Smuzhiyun	select SOC_TEGRA_PMC
18*4882a593Smuzhiyun	select SOC_TEGRA20_VOLTAGE_COUPLER
19*4882a593Smuzhiyun	select TEGRA_TIMER
20*4882a593Smuzhiyun	help
21*4882a593Smuzhiyun	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
22*4882a593Smuzhiyun	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
23*4882a593Smuzhiyun
24*4882a593Smuzhiyunconfig ARCH_TEGRA_3x_SOC
25*4882a593Smuzhiyun	bool "Enable support for Tegra30 family"
26*4882a593Smuzhiyun	select ARM_ERRATA_754322
27*4882a593Smuzhiyun	select ARM_ERRATA_764369 if SMP
28*4882a593Smuzhiyun	select PINCTRL_TEGRA30
29*4882a593Smuzhiyun	select PL310_ERRATA_769419 if CACHE_L2X0
30*4882a593Smuzhiyun	select SOC_TEGRA_FLOWCTRL
31*4882a593Smuzhiyun	select SOC_TEGRA_PMC
32*4882a593Smuzhiyun	select SOC_TEGRA30_VOLTAGE_COUPLER
33*4882a593Smuzhiyun	select TEGRA_TIMER
34*4882a593Smuzhiyun	help
35*4882a593Smuzhiyun	  Support for NVIDIA Tegra T30 processor family, based on the
36*4882a593Smuzhiyun	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
37*4882a593Smuzhiyun
38*4882a593Smuzhiyunconfig ARCH_TEGRA_114_SOC
39*4882a593Smuzhiyun	bool "Enable support for Tegra114 family"
40*4882a593Smuzhiyun	select ARM_ERRATA_798181 if SMP
41*4882a593Smuzhiyun	select HAVE_ARM_ARCH_TIMER
42*4882a593Smuzhiyun	select PINCTRL_TEGRA114
43*4882a593Smuzhiyun	select SOC_TEGRA_FLOWCTRL
44*4882a593Smuzhiyun	select SOC_TEGRA_PMC
45*4882a593Smuzhiyun	select TEGRA_TIMER
46*4882a593Smuzhiyun	help
47*4882a593Smuzhiyun	  Support for NVIDIA Tegra T114 processor family, based on the
48*4882a593Smuzhiyun	  ARM CortexA15MP CPU
49*4882a593Smuzhiyun
50*4882a593Smuzhiyunconfig ARCH_TEGRA_124_SOC
51*4882a593Smuzhiyun	bool "Enable support for Tegra124 family"
52*4882a593Smuzhiyun	select HAVE_ARM_ARCH_TIMER
53*4882a593Smuzhiyun	select PINCTRL_TEGRA124
54*4882a593Smuzhiyun	select SOC_TEGRA_FLOWCTRL
55*4882a593Smuzhiyun	select SOC_TEGRA_PMC
56*4882a593Smuzhiyun	select TEGRA_TIMER
57*4882a593Smuzhiyun	help
58*4882a593Smuzhiyun	  Support for NVIDIA Tegra T124 processor family, based on the
59*4882a593Smuzhiyun	  ARM CortexA15MP CPU
60*4882a593Smuzhiyun
61*4882a593Smuzhiyunendif
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun# 64-bit ARM SoCs
64*4882a593Smuzhiyunif ARM64
65*4882a593Smuzhiyun
66*4882a593Smuzhiyunconfig ARCH_TEGRA_132_SOC
67*4882a593Smuzhiyun	bool "NVIDIA Tegra132 SoC"
68*4882a593Smuzhiyun	select PINCTRL_TEGRA124
69*4882a593Smuzhiyun	select SOC_TEGRA_FLOWCTRL
70*4882a593Smuzhiyun	select SOC_TEGRA_PMC
71*4882a593Smuzhiyun	help
72*4882a593Smuzhiyun	  Enable support for NVIDIA Tegra132 SoC, based on the Denver
73*4882a593Smuzhiyun	  ARMv8 CPU.  The Tegra132 SoC is similar to the Tegra124 SoC,
74*4882a593Smuzhiyun	  but contains an NVIDIA Denver CPU complex in place of
75*4882a593Smuzhiyun	  Tegra124's "4+1" Cortex-A15 CPU complex.
76*4882a593Smuzhiyun
77*4882a593Smuzhiyunconfig ARCH_TEGRA_210_SOC
78*4882a593Smuzhiyun	bool "NVIDIA Tegra210 SoC"
79*4882a593Smuzhiyun	select PINCTRL_TEGRA210
80*4882a593Smuzhiyun	select SOC_TEGRA_FLOWCTRL
81*4882a593Smuzhiyun	select SOC_TEGRA_PMC
82*4882a593Smuzhiyun	select TEGRA_TIMER
83*4882a593Smuzhiyun	help
84*4882a593Smuzhiyun	  Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
85*4882a593Smuzhiyun	  the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
86*4882a593Smuzhiyun	  cores in a switched configuration. It features a GPU of the Maxwell
87*4882a593Smuzhiyun	  architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
88*4882a593Smuzhiyun	  and providing 256 CUDA cores. It supports hardware-accelerated en-
89*4882a593Smuzhiyun	  and decoding of various video standards including H.265, H.264 and
90*4882a593Smuzhiyun	  VP8 at 4K resolution and up to 60 fps.
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun	  Besides the multimedia features it also comes with a variety of I/O
93*4882a593Smuzhiyun	  controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
94*4882a593Smuzhiyun	  name only a few.
95*4882a593Smuzhiyun
96*4882a593Smuzhiyunconfig ARCH_TEGRA_186_SOC
97*4882a593Smuzhiyun	bool "NVIDIA Tegra186 SoC"
98*4882a593Smuzhiyun	select MAILBOX
99*4882a593Smuzhiyun	select TEGRA_BPMP
100*4882a593Smuzhiyun	select TEGRA_HSP_MBOX
101*4882a593Smuzhiyun	select TEGRA_IVC
102*4882a593Smuzhiyun	select SOC_TEGRA_PMC
103*4882a593Smuzhiyun	help
104*4882a593Smuzhiyun	  Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
105*4882a593Smuzhiyun	  combination of Denver and Cortex-A57 CPU cores and a GPU based on
106*4882a593Smuzhiyun	  the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
107*4882a593Smuzhiyun	  used for audio processing, hardware video encoders/decoders with
108*4882a593Smuzhiyun	  multi-format support, ISP for image capture processing and BPMP for
109*4882a593Smuzhiyun	  power management.
110*4882a593Smuzhiyun
111*4882a593Smuzhiyunconfig ARCH_TEGRA_194_SOC
112*4882a593Smuzhiyun	bool "NVIDIA Tegra194 SoC"
113*4882a593Smuzhiyun	select MAILBOX
114*4882a593Smuzhiyun	select PINCTRL_TEGRA194
115*4882a593Smuzhiyun	select TEGRA_BPMP
116*4882a593Smuzhiyun	select TEGRA_HSP_MBOX
117*4882a593Smuzhiyun	select TEGRA_IVC
118*4882a593Smuzhiyun	select SOC_TEGRA_PMC
119*4882a593Smuzhiyun	help
120*4882a593Smuzhiyun	  Enable support for the NVIDIA Tegra194 SoC.
121*4882a593Smuzhiyun
122*4882a593Smuzhiyunconfig ARCH_TEGRA_234_SOC
123*4882a593Smuzhiyun	bool "NVIDIA Tegra234 SoC"
124*4882a593Smuzhiyun	select MAILBOX
125*4882a593Smuzhiyun	select TEGRA_BPMP
126*4882a593Smuzhiyun	select TEGRA_HSP_MBOX
127*4882a593Smuzhiyun	select TEGRA_IVC
128*4882a593Smuzhiyun	select SOC_TEGRA_PMC
129*4882a593Smuzhiyun	help
130*4882a593Smuzhiyun	  Enable support for the NVIDIA Tegra234 SoC.
131*4882a593Smuzhiyun
132*4882a593Smuzhiyunendif
133*4882a593Smuzhiyunendif
134*4882a593Smuzhiyun
135*4882a593Smuzhiyunconfig SOC_TEGRA_FUSE
136*4882a593Smuzhiyun	def_bool y
137*4882a593Smuzhiyun	depends on ARCH_TEGRA
138*4882a593Smuzhiyun	select SOC_BUS
139*4882a593Smuzhiyun
140*4882a593Smuzhiyunconfig SOC_TEGRA_FLOWCTRL
141*4882a593Smuzhiyun	bool
142*4882a593Smuzhiyun
143*4882a593Smuzhiyunconfig SOC_TEGRA_PMC
144*4882a593Smuzhiyun	bool
145*4882a593Smuzhiyun	select GENERIC_PINCONF
146*4882a593Smuzhiyun
147*4882a593Smuzhiyunconfig SOC_TEGRA_POWERGATE_BPMP
148*4882a593Smuzhiyun	def_bool y
149*4882a593Smuzhiyun	depends on PM_GENERIC_DOMAINS
150*4882a593Smuzhiyun	depends on TEGRA_BPMP
151*4882a593Smuzhiyun
152*4882a593Smuzhiyunconfig SOC_TEGRA20_VOLTAGE_COUPLER
153*4882a593Smuzhiyun	bool "Voltage scaling support for Tegra20 SoCs"
154*4882a593Smuzhiyun	depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
155*4882a593Smuzhiyun
156*4882a593Smuzhiyunconfig SOC_TEGRA30_VOLTAGE_COUPLER
157*4882a593Smuzhiyun	bool "Voltage scaling support for Tegra30 SoCs"
158*4882a593Smuzhiyun	depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
159