1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun /* Tegra cache routines */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <asm/io.h>
11*4882a593Smuzhiyun #include <asm/arch-tegra/ap.h>
12*4882a593Smuzhiyun #include <asm/arch/gp_padctrl.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #ifndef CONFIG_ARM64
config_cache(void)15*4882a593Smuzhiyun void config_cache(void)
16*4882a593Smuzhiyun {
17*4882a593Smuzhiyun u32 reg = 0;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
20*4882a593Smuzhiyun asm volatile(
21*4882a593Smuzhiyun "mrc p15, 0, r0, c1, c0, 1\n"
22*4882a593Smuzhiyun "orr r0, r0, #0x41\n"
23*4882a593Smuzhiyun "mcr p15, 0, r0, c1, c0, 1\n");
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
26*4882a593Smuzhiyun if (tegra_get_chip() < CHIPID_TEGRA114)
27*4882a593Smuzhiyun return;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun * Systems with an architectural L2 cache must not use the PL310.
31*4882a593Smuzhiyun * Config L2CTLR here for a data RAM latency of 3 cycles.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
34*4882a593Smuzhiyun reg &= ~7;
35*4882a593Smuzhiyun reg |= 2;
36*4882a593Smuzhiyun asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun #endif
39