9 #include <asm/pl310.h>
42 	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;  in v7_outer_cache_enable()  local
51 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_enable()
55 	 * is cleared, PL310 treats Normal Shared Non-cacheable  in v7_outer_cache_enable()
58 	setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);  in v7_outer_cache_enable()
69 	writel(0x132, &pl310->pl310_tag_latency_ctrl);  in v7_outer_cache_enable()
70 	writel(0x132, &pl310->pl310_data_latency_ctrl);  in v7_outer_cache_enable()
72 	val = readl(&pl310->pl310_prefetch_ctrl);  in v7_outer_cache_enable()
78 	 * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0  in v7_outer_cache_enable()
79 	 * The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2  in v7_outer_cache_enable()
80 	 * But according to ARM PL310 errata: 752271  in v7_outer_cache_enable()
90 	writel(val, &pl310->pl310_prefetch_ctrl);  in v7_outer_cache_enable()
92 	val = readl(&pl310->pl310_power_ctrl);  in v7_outer_cache_enable()
95 	writel(val, &pl310->pl310_power_ctrl);  in v7_outer_cache_enable()
97 	setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_enable()
102 	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;  in v7_outer_cache_disable()  local
104 	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);  in v7_outer_cache_disable()