| /OK3568_Linux_fs/buildroot/package/am33x-cm3/ |
| H A D | 0001-fix-makefile.patch | 1 Enforce correct -march option
4 (which runs on a Cortex-M3 processor), but Buildroot will have a
5 default -march value that doesn't necessarily match the one needed for
6 Cortex-M3, leading to build failures (gcc complains that the
7 -mcpu=cortex-m3 option being passed is not compatible with the
8 selected -march).
10 Fix this by explicitly indicating -march=armv7-m.
12 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
16 Signed-off-by: Anders Darander <anders@chargestorm.se>
20 --- a/Makefile
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| H A D | am33x-cm3.mk | 3 # am33x-cm3
9 AM33X_CM3_SITE = http://arago-project.org/git/projects/am33x-cm3.git
14 # The build command below will use the standard cross-compiler (normally
15 # build for Cortex-A8, to build the FW for the Cortex-M3.
17 $(TARGET_MAKE_ENV) $(MAKE) CC="$(TARGET_CC)" CROSS_COMPILE="$(TARGET_CROSS)" -C $(@D) all
22 $(INSTALL) -m 0644 -D $(@D)/bin/am335x-pm-firmware.bin \
23 $(TARGET_DIR)/lib/firmware/am335x-pm-firmware.bin
27 $(INSTALL) -m 0755 -D package/am33x-cm3/S93-am335x-pm-firmware-load \
28 $(TARGET_DIR)/etc/init.d/S93-am335x-pm-firmware-load
31 $(eval $(generic-package))
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| H A D | Config.in | 2 bool "am33x-cm3"
6 Cortex-M3 binary blob for suspend-resume on am335x
8 http://arago-project.org/git/projects/am33x-cm3.git
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| H A D | 0003-Makefile-unconditionally-disable-PIE.patch | 6 Though -nostdlib is passed in $(CFLAGS), -fno-pie must also be passed to
11 - http://autobuild.buildroot.org/results/418a40b995e91bc66e692dfbc4b0521db3fa5fbb
13 Signed-off-by: Fabrice Fontaine <fontaine.fabrice@gmail.com>
14 ---
15 Makefile | 2 +-
16 1 file changed, 1 insertion(+), 1 deletion(-)
18 diff --git a/Makefile b/Makefile
20 --- a/Makefile
22 @@ -17,7 +17,7 @@ CFLAGS =-march=armv7-m -mcpu=cortex-m3 -mthumb -nostdlib -Wall -Wundef \
23 -Werror-implicit-function-declaration -Wstrict-prototypes \
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| /OK3568_Linux_fs/yocto/poky/meta/conf/machine/include/arm/armv7m/ |
| H A D | tune-cortexm3.inc | 2 # Tune Settings for Cortex-M3
6 TUNEVALID[cortexm3] = "Enable Cortex-M3 specific processor optimizations"
7 TUNE_CCARGS .= "${@bb.utils.contains('TUNE_FEATURES', 'cortexm3', ' -mcpu=cortex-m3', '', d)}"
9 require conf/machine/include/arm/arch-armv7m.inc
12 ARMPKGARCH:tune-cortexm3 = "cortexm3"
13 TUNE_FEATURES:tune-cortexm3 = "${TUNE_FEATURES:tune-armv7m} cortexm3"
14 PACKAGE_EXTRA_ARCHS:tune-cortexm3 = "${PACKAGE_EXTRA_ARCHS:tune-armv7m} cortexm3"
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| /OK3568_Linux_fs/kernel/arch/arm/mm/ |
| H A D | proc-v7m.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/mm/proc-v7m.S
8 * This is the "shell" of the ARMv7-M processor support.
14 #include "proc-macros.S"
31 * - loc - location to jump to for soft reset
104 * This should be able to cover all ARMv7-M cores.
140 ldmia sp, {r0-r3, r12}
144 @ Special-purpose control register
150 stmiane sp, {r0-r6, lr} @ v7m_invalidate_l1 touches r0-r6
152 teq r8, #0 @ re-evalutae condition
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/remoteproc/ |
| H A D | wkup_m3_rproc.txt | 1 TI Wakeup M3 Remoteproc Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
10 Wkup M3 Device Node:
12 A wkup_m3 device node is used to represent the Wakeup M3 processor instance
17 --------------------
18 - compatible: Should be one of,
19 "ti,am3352-wkup-m3" for AM33xx SoCs
20 "ti,am4372-wkup-m3" for AM43xx SoCs
21 - reg: Should contain the address ranges for the two internal
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/soc/ti/ |
| H A D | wkup_m3_ipc.txt | 1 Wakeup M3 IPC Driver
4 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
5 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
7 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
12 Wkup M3 Device Node:
18 --------------------
19 - compatible: Should be,
20 "ti,am3352-wkup-m3-ipc" for AM33xx SoCs
21 "ti,am4372-wkup-m3-ipc" for AM43xx SoCs
22 - reg: Contains the IPC register address space to communicate
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/infineon/bcmdhd/include/ |
| H A D | hndsoc.h | 2 * Broadcom HND chip & on-chip-interconnect-related definitions.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
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| H A D | sbhndarm.h | 6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: sbhndarm.h 699160 2017-05-12 04:50:25Z $
44 /* cortex-m3 */
77 #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg)
79 /* cortex-R4 */
111 #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg)
113 /* cortex-A7 */
127 #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg)
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| /OK3568_Linux_fs/external/rkwifibt/drivers/infineon/include/ |
| H A D | hndsoc.h | 2 * Broadcom HND chip & on-chip-interconnect-related definitions.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
[all …]
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| H A D | sbhndarm.h | 6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: sbhndarm.h 699160 2017-05-12 04:50:25Z $
44 /* cortex-m3 */
77 #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg)
79 /* cortex-R4 */
111 #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg)
113 /* cortex-A7 */
127 #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg)
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/ |
| H A D | hndsoc.h | 2 * Broadcom HND chip & on-chip-interconnect-related definitions.
6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $
70 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
75 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
76 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
89 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
94 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
104 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
[all …]
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| H A D | sbhndarm.h | 6 * Copyright (C) 1999-2017, Broadcom Corporation
27 * <<Broadcom-WL-IPTag/Open:>>
29 * $Id: sbhndarm.h 699160 2017-05-12 04:50:25Z $
44 /* cortex-m3 */
77 #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg)
79 /* cortex-R4 */
111 #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg)
113 /* cortex-A7 */
127 #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg)
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd_indep_power/include/ |
| H A D | hndsoc.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Broadcom HND chip & on-chip-interconnect-related definitions.
5 * Copyright (C) 1999-2017, Broadcom Corporation
26 * <<Broadcom-WL-IPTag/Open:>>
28 * $Id: hndsoc.h 613129 2016-01-17 09:25:52Z $
62 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
67 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
77 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
78 #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */
79 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
[all …]
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| /OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/ |
| H A D | sbhndarm.h | 21 * <<Broadcom-WL-IPTag/Dual:>>
109 /* arm core-specific control flags */
115 /* misc core-specific defines */
117 /* cortex-m3 */
123 #define ARMCM3_CYCLECNT 0x90 /**< Cortex-M3 core registers offsets */
129 #define ARMCM3_INTALL ((1 << ARMCM3_NUMINTS) - 1) /**< Interrupt mask */
157 /* cortex-r4 */
196 /* adjusted shift to fit 4-LSB (21 - 4 = 17) */
243 #define CHIP_SDRENABLE(sih) (sih->boardflags2 & BFL2_SDR_EN)
269 #define ARM_CLKGATING_CAP(sih) ((void)(sih), (BCM4378_CHIP(sih->chip) ||\
[all …]
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| H A D | hndsoc.h | 2 * Broadcom HND chip & on-chip-interconnect-related definitions.
21 * <<Broadcom-WL-IPTag/Dual:>>
60 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
66 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
67 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
71 #define SI_GPV_SL4_BM_ADDR 0x44024 /* NIC-400 Slave interface 4 Bypass merge */
72 #define SI_GPV_SL6_BM_ADDR 0x46024 /* NIC-400 Slave interface 6 Bypass merge */
73 #define SI_GPV_SL8_BM_ADDR 0x4a024 /* NIC-400 Slave interface 8 Bypass merge */
74 #define SI_GPV_SL9_BM_ADDR 0x4b024 /* NIC-400 Slave interface 9 Bypass merge */
95 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
[all …]
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| /OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/ |
| H A D | sbhndarm.h | 21 * <<Broadcom-WL-IPTag/Dual:>>
109 /* arm core-specific control flags */
115 /* misc core-specific defines */
117 /* cortex-m3 */
123 #define ARMCM3_CYCLECNT 0x90 /**< Cortex-M3 core registers offsets */
129 #define ARMCM3_INTALL ((1 << ARMCM3_NUMINTS) - 1) /**< Interrupt mask */
157 /* cortex-r4 */
196 /* adjusted shift to fit 4-LSB (21 - 4 = 17) */
243 #define CHIP_SDRENABLE(sih) (sih->boardflags2 & BFL2_SDR_EN)
269 #define ARM_CLKGATING_CAP(sih) ((void)(sih), (BCM4378_CHIP(sih->chip) ||\
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| H A D | hndsoc.h | 2 * Broadcom HND chip & on-chip-interconnect-related definitions.
21 * <<Broadcom-WL-IPTag/Dual:>>
60 #define SI_ENUM_BASE(sih) ((sih)->enum_base)
66 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */
67 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */
71 #define SI_GPV_SL4_BM_ADDR 0x44024 /* NIC-400 Slave interface 4 Bypass merge */
72 #define SI_GPV_SL6_BM_ADDR 0x46024 /* NIC-400 Slave interface 6 Bypass merge */
73 #define SI_GPV_SL8_BM_ADDR 0x4a024 /* NIC-400 Slave interface 8 Bypass merge */
74 #define SI_GPV_SL9_BM_ADDR 0x4b024 /* NIC-400 Slave interface 9 Bypass merge */
95 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
[all …]
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| /OK3568_Linux_fs/u-boot/arch/arm/cpu/armv7m/ |
| H A D | systick-timer.c | 2 * ARM Cortex M3/M4/M7 SysTick timer driver
5 * Based on arch/arm/mach-stm32/stm32f1/timer.c
12 * SPDX-License-Identifier: GPL-2.0+
14 * The SysTick timer is a 24-bit count down timer. The clock can be either the
30 /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
48 /* read the 24-bit timer */
54 return TIMER_MAX_VAL - readl(&systick->current_val); in read_timer()
62 writel(TIMER_MAX_VAL, &systick->reload_val); in timer_init()
64 writel(0, &systick->current_val); in timer_init()
66 cal = readl(&systick->calibration); in timer_init()
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| /OK3568_Linux_fs/kernel/drivers/soc/ti/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
2 # 64-bit ARM SoCs from TI
36 Packets are queued/de-queued by writing/reading descriptor address
58 c-states on AM335x. Also required for rtc and ddr in self-refresh low
62 tristate "TI AMx3 Wkup-M3 IPC Driver"
66 TI AM33XX and AM43XX have a Cortex M3, the Wakeup M3, to handle
68 to communicate and use the Wakeup M3 for PM features like suspend
105 tristate "TI PRU-ICSS Subsystem Platform drivers"
109 TI PRU-ICSS Subsystem platform specific support.
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| /OK3568_Linux_fs/buildroot/arch/ |
| H A D | Config.in.arm | 146 bool "arm1136j-s"
152 bool "arm1136jf-s"
159 bool "arm1176jz-s"
165 bool "arm1176jzf-s"
181 bool "cortex-A5"
189 bool "cortex-A7"
197 bool "cortex-A8"
205 bool "cortex-A9"
213 bool "cortex-A12"
221 bool "cortex-A15"
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| /OK3568_Linux_fs/kernel/arch/arm/mach-vexpress/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
24 This option enables support for systems using Cortex processor based
28 - CoreTile Express A5x2 (V2P-CA5s)
29 - CoreTile Express A9x4 (V2P-CA9)
30 - CoreTile Express A15x2 (V2P-CA15)
31 - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs
33 - Versatile Express RTSMs (Models)
42 bool "Enable A5 and A9 only errata work-arounds"
49 based on Cortex-A5 and Cortex-A9 processors. In order to
68 between the dual cluster test-chip and the M3 microcontroller that
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-rockchip/rk3288/ |
| H A D | Kconfig | 4 bool "Google/Rockchip Veyron-Jerry Chromebook"
7 Jerry is a RK3288-based clamshell device with 2 USB 3.0 ports,
8 HDMI, an 11.9 inch EDP display, micro-SD card, touchpad and
9 WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
13 bool "Google/Rockchip Veyron-Mickey Chromebit"
16 Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
23 bool "Google/Rockchip Veyron-Minnie Chromebook"
26 Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0
27 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card,
29 EC (Cortex-M3) to provide access to the keyboard and battery
[all …]
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mailbox/ |
| H A D | xgene-slimpro-mailbox.txt | 1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
2 the ARM64 processors and the Cortex M3 (dubbed SLIMpro). It uses a simple
10 - compatible: Should be as "apm,xgene-slimpro-mbox".
12 - reg: Contains the mailbox register address range.
14 - interrupts: 8 interrupts must be from 0 to 7, interrupt 0 define the
18 - #mbox-cells: only one to specify the mailbox channel number.
24 compatible = "apm,xgene-slimpro-mbox";
26 #mbox-cells = <1>;
|