1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyunmenuconfig ARCH_VEXPRESS 3*4882a593Smuzhiyun bool "ARM Ltd. Versatile Express family" 4*4882a593Smuzhiyun depends on ARCH_MULTI_V7 5*4882a593Smuzhiyun select ARCH_SUPPORTS_BIG_ENDIAN 6*4882a593Smuzhiyun select ARM_AMBA 7*4882a593Smuzhiyun select ARM_GIC 8*4882a593Smuzhiyun select ARM_GLOBAL_TIMER 9*4882a593Smuzhiyun select ARM_TIMER_SP804 10*4882a593Smuzhiyun select GPIOLIB 11*4882a593Smuzhiyun select HAVE_ARM_SCU if SMP 12*4882a593Smuzhiyun select HAVE_ARM_TWD if SMP 13*4882a593Smuzhiyun select HAVE_PATA_PLATFORM 14*4882a593Smuzhiyun select ICST 15*4882a593Smuzhiyun select NO_IOPORT_MAP 16*4882a593Smuzhiyun select PLAT_VERSATILE 17*4882a593Smuzhiyun select POWER_RESET 18*4882a593Smuzhiyun select POWER_RESET_VEXPRESS 19*4882a593Smuzhiyun select POWER_SUPPLY 20*4882a593Smuzhiyun select REGULATOR if MMC_ARMMMCI 21*4882a593Smuzhiyun select REGULATOR_FIXED_VOLTAGE if REGULATOR 22*4882a593Smuzhiyun select VEXPRESS_CONFIG 23*4882a593Smuzhiyun help 24*4882a593Smuzhiyun This option enables support for systems using Cortex processor based 25*4882a593Smuzhiyun ARM core and logic (FPGA) tiles on the Versatile Express motherboard, 26*4882a593Smuzhiyun for example: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun - CoreTile Express A5x2 (V2P-CA5s) 29*4882a593Smuzhiyun - CoreTile Express A9x4 (V2P-CA9) 30*4882a593Smuzhiyun - CoreTile Express A15x2 (V2P-CA15) 31*4882a593Smuzhiyun - LogicTile Express 13MG (V2F-2XV6) with A5, A7, A9 or A15 SMMs 32*4882a593Smuzhiyun (Soft Macrocell Models) 33*4882a593Smuzhiyun - Versatile Express RTSMs (Models) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun You must boot using a Flattened Device Tree in order to use these 36*4882a593Smuzhiyun platforms. The traditional (ATAGs) boot method is not usable on 37*4882a593Smuzhiyun these boards with this option. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunif ARCH_VEXPRESS 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunconfig ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA 42*4882a593Smuzhiyun bool "Enable A5 and A9 only errata work-arounds" 43*4882a593Smuzhiyun default y 44*4882a593Smuzhiyun select ARM_ERRATA_643719 if SMP 45*4882a593Smuzhiyun select ARM_ERRATA_720789 46*4882a593Smuzhiyun select PL310_ERRATA_753970 if CACHE_L2X0 47*4882a593Smuzhiyun help 48*4882a593Smuzhiyun Provides common dependencies for Versatile Express platforms 49*4882a593Smuzhiyun based on Cortex-A5 and Cortex-A9 processors. In order to 50*4882a593Smuzhiyun build a working kernel, you must also enable relevant core 51*4882a593Smuzhiyun tile support or Flattened Device Tree based support options. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyunconfig ARCH_VEXPRESS_DCSCB 54*4882a593Smuzhiyun bool "Dual Cluster System Control Block (DCSCB) support" 55*4882a593Smuzhiyun depends on MCPM 56*4882a593Smuzhiyun select ARM_CCI400_PORT_CTRL 57*4882a593Smuzhiyun help 58*4882a593Smuzhiyun Support for the Dual Cluster System Configuration Block (DCSCB). 59*4882a593Smuzhiyun This is needed to provide CPU and cluster power management 60*4882a593Smuzhiyun on RTSM implementing big.LITTLE. 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunconfig ARCH_VEXPRESS_SPC 63*4882a593Smuzhiyun bool "Versatile Express Serial Power Controller (SPC)" 64*4882a593Smuzhiyun select PM_OPP 65*4882a593Smuzhiyun help 66*4882a593Smuzhiyun The TC2 (A15x2 A7x3) versatile express core tile integrates a logic 67*4882a593Smuzhiyun block called Serial Power Controller (SPC) that provides the interface 68*4882a593Smuzhiyun between the dual cluster test-chip and the M3 microcontroller that 69*4882a593Smuzhiyun carries out power management. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunconfig ARCH_VEXPRESS_TC2_PM 72*4882a593Smuzhiyun bool "Versatile Express TC2 power management" 73*4882a593Smuzhiyun depends on MCPM 74*4882a593Smuzhiyun select ARM_CCI400_PORT_CTRL 75*4882a593Smuzhiyun select ARCH_VEXPRESS_SPC 76*4882a593Smuzhiyun select ARM_CPU_SUSPEND 77*4882a593Smuzhiyun help 78*4882a593Smuzhiyun Support for CPU and cluster power management on Versatile Express 79*4882a593Smuzhiyun with a TC2 (A15x2 A7x3) big.LITTLE core tile. 80*4882a593Smuzhiyun 81*4882a593Smuzhiyunendif 82