1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Broadcom SiliconBackplane ARM definitions 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Portions of this code are copyright (c) 2021 Cypress Semiconductor Corporation 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 1999-2017, Broadcom Corporation 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Unless you and Broadcom execute a separate written software license 9*4882a593Smuzhiyun * agreement governing use of this software, this software is licensed to you 10*4882a593Smuzhiyun * under the terms of the GNU General Public License version 2 (the "GPL"), 11*4882a593Smuzhiyun * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12*4882a593Smuzhiyun * following added to such license: 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * As a special exception, the copyright holders of this software give you 15*4882a593Smuzhiyun * permission to link this software with independent modules, and to copy and 16*4882a593Smuzhiyun * distribute the resulting executable under terms of your choice, provided that 17*4882a593Smuzhiyun * you also meet, for each linked independent module, the terms and conditions of 18*4882a593Smuzhiyun * the license of that module. An independent module is a module which is not 19*4882a593Smuzhiyun * derived from this software. The special exception does not apply to any 20*4882a593Smuzhiyun * modifications of the software. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * Notwithstanding the above, under no circumstances may you combine this 23*4882a593Smuzhiyun * software in any way with any other Broadcom software provided under a license 24*4882a593Smuzhiyun * other than the GPL, without Broadcom's express prior written consent. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * 27*4882a593Smuzhiyun * <<Broadcom-WL-IPTag/Open:>> 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * $Id: sbhndarm.h 699160 2017-05-12 04:50:25Z $ 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #ifndef _sbhndarm_h_ 33*4882a593Smuzhiyun #define _sbhndarm_h_ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef _LANGUAGE_ASSEMBLY 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* cpp contortions to concatenate w/arg prescan */ 38*4882a593Smuzhiyun #ifndef PAD 39*4882a593Smuzhiyun #define _PADLINE(line) pad ## line 40*4882a593Smuzhiyun #define _XSTR(line) _PADLINE(line) 41*4882a593Smuzhiyun #define PAD _XSTR(__LINE__) 42*4882a593Smuzhiyun #endif /* PAD */ 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* cortex-m3 */ 45*4882a593Smuzhiyun typedef volatile struct { 46*4882a593Smuzhiyun uint32 corecontrol; /* 0x0 */ 47*4882a593Smuzhiyun uint32 corestatus; /* 0x4 */ 48*4882a593Smuzhiyun uint32 PAD[1]; 49*4882a593Smuzhiyun uint32 biststatus; /* 0xc */ 50*4882a593Smuzhiyun uint32 nmiisrst; /* 0x10 */ 51*4882a593Smuzhiyun uint32 nmimask; /* 0x14 */ 52*4882a593Smuzhiyun uint32 isrmask; /* 0x18 */ 53*4882a593Smuzhiyun uint32 PAD[1]; 54*4882a593Smuzhiyun uint32 resetlog; /* 0x20 */ 55*4882a593Smuzhiyun uint32 gpioselect; /* 0x24 */ 56*4882a593Smuzhiyun uint32 gpioenable; /* 0x28 */ 57*4882a593Smuzhiyun uint32 PAD[1]; 58*4882a593Smuzhiyun uint32 bpaddrlo; /* 0x30 */ 59*4882a593Smuzhiyun uint32 bpaddrhi; /* 0x34 */ 60*4882a593Smuzhiyun uint32 bpdata; /* 0x38 */ 61*4882a593Smuzhiyun uint32 bpindaccess; /* 0x3c */ 62*4882a593Smuzhiyun uint32 ovlidx; /* 0x40 */ 63*4882a593Smuzhiyun uint32 ovlmatch; /* 0x44 */ 64*4882a593Smuzhiyun uint32 ovladdr; /* 0x48 */ 65*4882a593Smuzhiyun uint32 PAD[13]; 66*4882a593Smuzhiyun uint32 bwalloc; /* 0x80 */ 67*4882a593Smuzhiyun uint32 PAD[3]; 68*4882a593Smuzhiyun uint32 cyclecnt; /* 0x90 */ 69*4882a593Smuzhiyun uint32 inttimer; /* 0x94 */ 70*4882a593Smuzhiyun uint32 intmask; /* 0x98 */ 71*4882a593Smuzhiyun uint32 intstatus; /* 0x9c */ 72*4882a593Smuzhiyun uint32 PAD[80]; 73*4882a593Smuzhiyun uint32 clk_ctl_st; /* 0x1e0 */ 74*4882a593Smuzhiyun uint32 PAD[1]; 75*4882a593Smuzhiyun uint32 powerctl; /* 0x1e8 */ 76*4882a593Smuzhiyun } cm3regs_t; 77*4882a593Smuzhiyun #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* cortex-R4 */ 80*4882a593Smuzhiyun typedef volatile struct { 81*4882a593Smuzhiyun uint32 corecontrol; /* 0x0 */ 82*4882a593Smuzhiyun uint32 corecapabilities; /* 0x4 */ 83*4882a593Smuzhiyun uint32 corestatus; /* 0x8 */ 84*4882a593Smuzhiyun uint32 biststatus; /* 0xc */ 85*4882a593Smuzhiyun uint32 nmiisrst; /* 0x10 */ 86*4882a593Smuzhiyun uint32 nmimask; /* 0x14 */ 87*4882a593Smuzhiyun uint32 isrmask; /* 0x18 */ 88*4882a593Smuzhiyun uint32 swintreg; /* 0x1C */ 89*4882a593Smuzhiyun uint32 intstatus; /* 0x20 */ 90*4882a593Smuzhiyun uint32 intmask; /* 0x24 */ 91*4882a593Smuzhiyun uint32 cyclecnt; /* 0x28 */ 92*4882a593Smuzhiyun uint32 inttimer; /* 0x2c */ 93*4882a593Smuzhiyun uint32 gpioselect; /* 0x30 */ 94*4882a593Smuzhiyun uint32 gpioenable; /* 0x34 */ 95*4882a593Smuzhiyun uint32 PAD[2]; 96*4882a593Smuzhiyun uint32 bankidx; /* 0x40 */ 97*4882a593Smuzhiyun uint32 bankinfo; /* 0x44 */ 98*4882a593Smuzhiyun uint32 bankstbyctl; /* 0x48 */ 99*4882a593Smuzhiyun uint32 bankpda; /* 0x4c */ 100*4882a593Smuzhiyun uint32 PAD[6]; 101*4882a593Smuzhiyun uint32 tcampatchctrl; /* 0x68 */ 102*4882a593Smuzhiyun uint32 tcampatchtblbaseaddr; /* 0x6c */ 103*4882a593Smuzhiyun uint32 tcamcmdreg; /* 0x70 */ 104*4882a593Smuzhiyun uint32 tcamdatareg; /* 0x74 */ 105*4882a593Smuzhiyun uint32 tcambankxmaskreg; /* 0x78 */ 106*4882a593Smuzhiyun uint32 PAD[89]; 107*4882a593Smuzhiyun uint32 clk_ctl_st; /* 0x1e0 */ 108*4882a593Smuzhiyun uint32 PAD[1]; 109*4882a593Smuzhiyun uint32 powerctl; /* 0x1e8 */ 110*4882a593Smuzhiyun } cr4regs_t; 111*4882a593Smuzhiyun #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* cortex-A7 */ 114*4882a593Smuzhiyun typedef volatile struct { 115*4882a593Smuzhiyun uint32 corecontrol; /* 0x0 */ 116*4882a593Smuzhiyun uint32 corecapabilities; /* 0x4 */ 117*4882a593Smuzhiyun uint32 corestatus; /* 0x8 */ 118*4882a593Smuzhiyun uint32 tracecontrol; /* 0xc */ 119*4882a593Smuzhiyun uint32 PAD[8]; 120*4882a593Smuzhiyun uint32 gpioselect; /* 0x30 */ 121*4882a593Smuzhiyun uint32 gpioenable; /* 0x34 */ 122*4882a593Smuzhiyun uint32 PAD[106]; 123*4882a593Smuzhiyun uint32 clk_ctl_st; /* 0x1e0 */ 124*4882a593Smuzhiyun uint32 PAD[1]; 125*4882a593Smuzhiyun uint32 powerctl; /* 0x1e8 */ 126*4882a593Smuzhiyun } ca7regs_t; 127*4882a593Smuzhiyun #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #if defined(__ARM_ARCH_7M__) 130*4882a593Smuzhiyun #define ARMREG(regs, reg) ARM_CM3_REG(regs, reg) 131*4882a593Smuzhiyun #endif /* __ARM_ARCH_7M__ */ 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #if defined(__ARM_ARCH_7R__) 134*4882a593Smuzhiyun #define ARMREG(regs, reg) ARM_CR4_REG(regs, reg) 135*4882a593Smuzhiyun #endif /* __ARM_ARCH_7R__ */ 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #if defined(__ARM_ARCH_7A__) 138*4882a593Smuzhiyun #define ARMREG(regs, reg) ARM_CA7_REG(regs, reg) 139*4882a593Smuzhiyun #endif /* __ARM_ARCH_7A__ */ 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #endif /* _LANGUAGE_ASSEMBLY */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun #endif /* _sbhndarm_h_ */ 144