1 /* 2 * Broadcom SiliconBackplane ARM definitions 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _sbhndarm_h_ 25 #define _sbhndarm_h_ 26 27 #ifdef DONGLEBUILD 28 29 #include <arminc.h> 30 #include <sbconfig.h> 31 32 /* register offsets */ 33 #define ARM7_CORECTL 0 34 35 /* bits in corecontrol */ 36 #define ACC_FORCED_RST 0x1 37 #define ACC_SERRINT 0x2 38 #define ACC_WFICLKSTOP 0x4 39 40 #if !defined(__ARM_ARCH_7A__) 41 #define ACC_NOTSLEEPINGCLKREQ_SHIFT 24 42 #endif /* !__ARM_ARCH_7A__ */ 43 44 #if defined(__ARM_ARCH_7A__) 45 46 #define ACC_FORCECLOCKRATIO (0x1u << 8) 47 #define ACC_CLOCKRATIO_SHIFT (9u) 48 #define ACC_CLOCKRATIO_MASK (0xFu << ACC_CLOCKRATIO_SHIFT) 49 50 #define ACC_CLOCKRATIO_1_TO_1 (0u) 51 #define ACC_CLOCKRATIO_2_TO_1 (1u) 52 #define ACC_CLOCKRATIO_3_TO_1 (2u) 53 #define ACC_CLOCKRATIO_4_TO_1 (3u) 54 55 #define ACC_FASTCLOCKCHANNEL_SHIFT (24u) 56 #define ACC_FASTCLOCKCHANNEL_MASK (0x3u << ACC_FASTCLOCKCHANNEL_SHIFT) 57 #define ACC_NUM_FASTCLOCKS_SHIFT (2u) 58 #define ACC_NUM_FASTCLOCKS_MASK (0x3u << ACC_NUM_FASTCLOCKS_SHIFT) 59 60 #define ACC_NOTSLEEPINGCLKREQ_SHIFT (4u) 61 #define ACC_NOTSLEEPINGCLKREQ_MASK (0x3u << ACC_NOT_SLEEPING_CLKREQ_SHIFT) 62 #define ACC_NOTSLEEPING_ALP (0u) 63 #define ACC_NOTSLEEPING_HT (1u) 64 #define ACC_NOTSLEEPING_ALP_HT_AVAIL (2u) 65 #define ACC_NOTSLEEPING_HT_AVAIL (3u) 66 67 #elif defined(__ARM_ARCH_7R__) /* CR4 */ 68 69 #define ACC_FORCECLOCKRATIO (1u << 7u) 70 #define ACC_CLOCKRATIO_SHIFT 8u 71 #define ACC_CLOCKRATIO_MASK (0xFu << ACC_CLOCKRATIO_SHIFT) 72 #define ACC_CLOCKMODE_SHIFT 12u 73 #define ACC_CLOCKMODE_MASK (7u << ACC_CLOCKMODE_SHIFT) 74 #define ACC_NOTSLEEPCLKREQ0 3u 75 #define ACC_NOTSLEEPCLKREQ1 18u 76 #define ACC_FLOPSPROTECT (1u << 20u) 77 78 #define ACC_CLOCKRATIO_1_TO_1 (0u) 79 #define ACC_CLOCKRATIO_2_TO_1 (4u) 80 81 #endif /* __ARM_ARCH_7A__ */ 82 83 #define ACC_CLOCKMODE_SAME (0) /**< BP and CPU clock are the same */ 84 #define ACC_CLOCKMODE_ASYNC (1) /**< BP and CPU clock are asynchronous */ 85 #define ACC_CLOCKMODE_SYNCH (2) /**< BP and CPU clock are synch, ratio 1:1 or 1:2 */ 86 87 /* Request ALP on backplane bit 3 and 18 */ 88 #define ACC_REQALP ((1<<ACC_NOTSLEEPCLKREQ0) | (1<<ACC_NOTSLEEPCLKREQ1)) 89 90 #define ACC_MPU_SHIFT 25u 91 #define ACC_MPU_MASK (0x1u << ACC_MPU_SHIFT) 92 93 #define ACC_MPU_REGION_CNT_MASK 0x7u 94 #define ACC_MPU_REGION_CNT_SHIFT 3u 95 96 #define ACC_MPU_SECURE_SHIFT 27u 97 #define ACC_MPU_SECURE_MASK (0x1u << ACC_MPU_SECURE_SHIFT) 98 #define ACC_MPU_READ_SHIFT 30u 99 #define ACC_MPU_READ_MASK (0x1u << ACC_MPU_READ_SHIFT) 100 #define ACC_MPU_WRITE_SHIFT 29u 101 #define ACC_MPU_WRITE_MASK (0x1u << ACC_MPU_WRITE_SHIFT) 102 #define ACC_MPU_VALID_SHIFT 31u 103 #define ACC_MPU_VALID_MASK (0x1u << ACC_MPU_VALID_SHIFT) 104 105 /* arm resetlog */ 106 #define SBRESETLOG 0x1 107 #define SERRORLOG 0x2 108 109 /* arm core-specific control flags */ 110 #define SICF_REMAP_MSK 0x001c 111 #define SICF_REMAP_NONE 0 112 #define SICF_REMAP_ROM 0x0004 113 #define SIFC_REMAP_FLASH 0x0008 114 115 /* misc core-specific defines */ 116 #if defined(__ARM_ARCH_7M__) 117 /* cortex-m3 */ 118 /* backplane related stuff */ 119 #define ARM_CORE_ID ARMCM3_CORE_ID /**< arm coreid */ 120 #define SI_ARM_ROM SI_ARMCM3_ROM /**< ROM backplane/system address */ 121 #define SI_ARM_SRAM2 SI_ARMCM3_SRAM2 /**< RAM backplane address when remap is 1 or 2 */ 122 /* core registers offsets */ 123 #define ARMCM3_CYCLECNT 0x90 /**< Cortex-M3 core registers offsets */ 124 #define ARMCM3_INTTIMER 0x94 125 #define ARMCM3_INTMASK 0x98 126 #define ARMCM3_INTSTATUS 0x9c 127 /* interrupt/exception */ 128 #define ARMCM3_NUMINTS 16 /**< # of external interrupts */ 129 #define ARMCM3_INTALL ((1 << ARMCM3_NUMINTS) - 1) /**< Interrupt mask */ 130 #define ARMCM3_SHARED_INT 0 /**< Interrupt shared by multiple cores */ 131 #define ARMCM3_INT(i) (1 << (i)) /**< Individual interrupt enable/disable */ 132 /* intmask/intstatus bits */ 133 #define ARMCM3_INTMASK_TIMER 0x1 134 #define ARMCM3_INTMASK_SYSRESET 0x4 135 #define ARMCM3_INTMASK_LOCKUP 0x8 136 137 /* 138 * Overlay Support in Rev 5 139 */ 140 #define ARMCM3_OVL_VALID_SHIFT 0 141 #define ARMCM3_OVL_VALID 1 142 #define ARMCM3_OVL_SZ_SHIFT 1 143 #define ARMCM3_OVL_SZ_MASK 0x0000000e 144 #define ARMCM3_OVL_SZ_512B 0 /* 512B */ 145 #define ARMCM3_OVL_SZ_1KB 1 /* 1KB */ 146 #define ARMCM3_OVL_SZ_2KB 2 /* 2KB */ 147 #define ARMCM3_OVL_SZ_4KB 3 /* 4KB */ 148 #define ARMCM3_OVL_SZ_8KB 4 /* 8KB */ 149 #define ARMCM3_OVL_SZ_16KB 5 /* 16KB */ 150 #define ARMCM3_OVL_SZ_32KB 6 /* 32KB */ 151 #define ARMCM3_OVL_SZ_64KB 7 /* 64KB */ 152 #define ARMCM3_OVL_ADDR_SHIFT 9 153 #define ARMCM3_OVL_ADDR_MASK 0x003FFE00 154 #define ARMCM3_OVL_MAX 16 155 156 #elif defined(__ARM_ARCH_7R__) 157 /* cortex-r4 */ 158 /* backplane related stuff */ 159 #define ARM_CORE_ID ARMCR4_CORE_ID /**< arm coreid */ 160 #define SI_ARM_ROM SI_ARMCR4_ROM /**< ROM backplane/system address */ 161 #define SI_ARM_SRAM2 0x0 /**< In the cr4 the RAM is just not available 162 * when remap is 1 163 */ 164 165 /* core registers offsets */ 166 #define ARMCR4_CORECTL 0 167 #define ARMCR4_CORECAP 4 168 #define ARMCR4_COREST 8 169 170 #define ARMCR4_FIQRSTATUS 0x10 171 #define ARMCR4_FIQMASK 0x14 172 #define ARMCR4_IRQMASK 0x18 173 174 #define ARMCR4_INTSTATUS 0x20 175 #define ARMCR4_INTMASK 0x24 176 #define ARMCR4_CYCLECNT 0x28 177 #define ARMCR4_INTTIMER 0x2c 178 179 #define ARMCR4_GPIOSEL 0x30 180 #define ARMCR4_GPIOEN 0x34 181 182 #define ARMCR4_BANKIDX 0x40 183 #define ARMCR4_BANKINFO 0x44 184 #define ARMCR4_BANKSTBY 0x48 185 #define ARMCR4_BANKPDA 0x4c 186 187 #define ARMCR4_TCAMPATCHCTRL 0x68 188 #define ARMCR4_TCAMPATCHTBLBASEADDR 0x6C 189 #define ARMCR4_TCAMCMDREG 0x70 190 #define ARMCR4_TCAMDATAREG 0x74 191 #define ARMCR4_TCAMBANKXMASKREG 0x78 192 193 #define ARMCR4_ROMNB_MASK 0xf00 194 #define ARMCR4_ROMNB_SHIFT 8 195 #define ARMCR4_MSB_ROMNB_MASK 0x1E00000 196 /* adjusted shift to fit 4-LSB (21 - 4 = 17) */ 197 #define ARMCR4_MSB_ROMNB_SHIFT 17 198 #define ARMCR4_TCBBNB_MASK 0xf0 199 #define ARMCR4_TCBBNB_SHIFT 4 200 #define ARMCR4_TCBANB_MASK 0xf 201 #define ARMCR4_TCBANB_SHIFT 0 202 203 #define ARMCR4_MT_MASK 0x300 204 #define ARMCR4_MT_SHIFT 8 205 #define ARMCR4_MT_ROM 0x100 206 #define ARMCR4_MT_RAM 0 207 208 #define ARMCR4_BSZ_MASK 0x7f 209 #define ARMCR4_BUNITSZ_MASK 0x200 210 #define ARMCR4_BSZ_8K 8192 211 #define ARMCR4_BSZ_1K 1024 212 213 #define ARMCR4_STBY_SUPPORTED 0x400 214 #define ARMCR4_STBY_TIMER_PRESENT 0x800 215 216 #define ARMCR4_TIMER_VAL_MASK 0xfffff 217 #define ARMCR4_STBY_TIMER_ENABLE (1 << 24) 218 #define ARMCR4_STBY_OVERRIDE (1 << 31) 219 220 #define ARMCR4_TCAM_ENABLE (1u << 31u) 221 #define ARMCR4_TCAM_CLKENAB (1u << 30u) 222 #define ARMCR4_TCAM_WRITEPROT (1u << 29u) 223 #define ARMCR4_TCAM_PATCHCNT_MASK 0xfu 224 225 #define ARMCR4_TCAM_CMD_DONE (1u << 31) 226 #define ARMCR4_TCAM_MATCH (1u << 24) 227 #define ARMCR4_TCAM_OPCODE_MASK (3 << 16) 228 #define ARMCR4_TCAM_OPCODE_SHIFT 16 229 #define ARMCR4_TCAM_ADDR_MASK 0xffff 230 #define ARMCR4_TCAM_NONE (0 << ARMCR4_TCAM_OPCODE_SHIFT) 231 #define ARMCR4_TCAM_READ (1 << ARMCR4_TCAM_OPCODE_SHIFT) 232 #define ARMCR4_TCAM_WRITE (2 << ARMCR4_TCAM_OPCODE_SHIFT) 233 #define ARMCR4_TCAM_COMPARE (3 << ARMCR4_TCAM_OPCODE_SHIFT) 234 #define ARMCR4_TCAM_CMD_DONE_DLY 1000 235 236 #define ARMCR4_DATA_MASK (~0x7) 237 #define ARMCR4_DATA_VALID (1u << 0) 238 239 /* intmask/intstatus bits */ 240 #define ARMCR4_INTMASK_TIMER (0x1) 241 #define ARMCR4_INTMASK_CLOCKSTABLE (0x20000000) 242 243 #define CHIP_SDRENABLE(sih) (sih->boardflags2 & BFL2_SDR_EN) 244 #define CHIP_TCMPROTENAB(sih) (si_arm_sflags(sih) & SISF_TCMPROT) 245 246 /* Power Control */ 247 #define ARM_ENAB_MEM_CLK_GATE_SHIFT 5 248 249 #define ROM_STBY_TIMER_4378 0xb0 250 #define RAM_STBY_TIMER_4378 0x64 251 252 #define ROM_STBY_TIMER_4387 0x10 253 #define RAM_STBY_TIMER_4387 0x100 254 255 #define RAM_STBY_DEFAULT_WAIT_TIME (3u) 256 #define ROM_STBY_DEFAULT_WAIT_TIME (4u) 257 #define DEFAULT_FORCE_STBY_IN_WFI (1u) 258 #define ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_SHIFT (0u) 259 #define ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_MASK (0xF << \ 260 ARMCR4_DYN_STBY_CTRL_RAM_STBY_WAIT_TIMER_SHIFT) 261 #define ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_SHIFT (8u) 262 #define ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_MASK (0x3F << \ 263 ARMCR4_DYN_STBY_CTRL_ROM_STBY_WAIT_TIMER_SHIFT) 264 #define ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_SHIFT (16u) 265 #define ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_MASK (0x1 << \ 266 ARMCR4_DYN_STBY_CTRL_FORCE_STBY_IN_WFI_SHIFT) 267 268 /* using CHIPID because no capabilities bit */ 269 #define ARM_CLKGATING_CAP(sih) ((void)(sih), (BCM4378_CHIP(sih->chip) ||\ 270 BCM4387_CHIP(sih->chip))) 271 272 #define ARM_CLKGATING_ENAB(sih) (ARM_CLKGATING_CAP(sih) && 1) 273 274 #elif defined(__ARM_ARCH_7A__) 275 276 #if defined(CA7) 277 /* backplane related stuff */ 278 #define ARM_CORE_ID ARMCA7_CORE_ID 279 #define SI_ARM_ROM SI_ARMCA7_ROM /**< ROM backplane/system address */ 280 281 #else 282 /* backplane related stuff */ 283 #define ARM_CORE_ID ARMCA9_CORE_ID /* arm coreid */ 284 #endif /* __ARM_ARCH_7A__ */ 285 #else /* !__ARM_ARCH_7M__ && !__ARM_ARCH_7R__ */ 286 #error Unrecognized ARM Architecture 287 #endif /* !__ARM_ARCH_7M__ && !__ARM_ARCH_7R__ */ 288 289 #endif /* DONGLEBUILD */ 290 291 #ifndef _LANGUAGE_ASSEMBLY 292 293 /* cpp contortions to concatenate w/arg prescan */ 294 #ifndef PAD 295 #define _PADLINE(line) pad ## line 296 #define _XSTR(line) _PADLINE(line) 297 #define PAD _XSTR(__LINE__) 298 #endif /* PAD */ 299 300 /* cortex-m3 */ 301 typedef volatile struct { 302 uint32 corecontrol; /* 0x0 */ 303 uint32 corestatus; /* 0x4 */ 304 uint32 PAD[1]; 305 uint32 biststatus; /* 0xc */ 306 uint32 nmiisrst; /* 0x10 */ 307 uint32 nmimask; /* 0x14 */ 308 uint32 isrmask; /* 0x18 */ 309 uint32 PAD[1]; 310 uint32 resetlog; /* 0x20 */ 311 uint32 gpioselect; /* 0x24 */ 312 uint32 gpioenable; /* 0x28 */ 313 uint32 PAD[1]; 314 uint32 bpaddrlo; /* 0x30 */ 315 uint32 bpaddrhi; /* 0x34 */ 316 uint32 bpdata; /* 0x38 */ 317 uint32 bpindaccess; /* 0x3c */ 318 uint32 ovlidx; /* 0x40 */ 319 uint32 ovlmatch; /* 0x44 */ 320 uint32 ovladdr; /* 0x48 */ 321 uint32 PAD[13]; 322 uint32 bwalloc; /* 0x80 */ 323 uint32 PAD[3]; 324 uint32 cyclecnt; /* 0x90 */ 325 uint32 inttimer; /* 0x94 */ 326 uint32 intmask; /* 0x98 */ 327 uint32 intstatus; /* 0x9c */ 328 uint32 PAD[80]; 329 uint32 clk_ctl_st; /* 0x1e0 */ 330 uint32 PAD[1]; 331 uint32 powerctl; /* 0x1e8 */ 332 } cm3regs_t; 333 #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg) 334 335 /* cortex-R4 */ 336 typedef volatile struct { 337 uint32 corecontrol; /* 0x0 */ 338 uint32 corecapabilities; /* 0x4 */ 339 uint32 corestatus; /* 0x8 */ 340 uint32 biststatus; /* 0xc */ 341 uint32 nmiisrst; /* 0x10 */ 342 uint32 nmimask; /* 0x14 */ 343 uint32 isrmask; /* 0x18 */ 344 uint32 swintreg; /* 0x1C */ 345 uint32 intstatus; /* 0x20 */ 346 uint32 intmask; /* 0x24 */ 347 uint32 cyclecnt; /* 0x28 */ 348 uint32 inttimer; /* 0x2c */ 349 uint32 gpioselect; /* 0x30 */ 350 uint32 gpioenable; /* 0x34 */ 351 uint32 PAD[2]; 352 uint32 bankidx; /* 0x40 */ 353 uint32 bankinfo; /* 0x44 */ 354 uint32 bankstbyctl; /* 0x48 */ 355 uint32 bankpda; /* 0x4c */ 356 uint32 dyn_stby_control; /* 0x50 */ 357 uint32 PAD[5]; 358 uint32 tcampatchctrl; /* 0x68 */ 359 uint32 tcampatchtblbaseaddr; /* 0x6c */ 360 uint32 tcamcmdreg; /* 0x70 */ 361 uint32 tcamdatareg; /* 0x74 */ 362 uint32 tcambankxmaskreg; /* 0x78 */ 363 uint32 PAD[5]; 364 uint32 mpucontrol; /* 0x90 */ 365 uint32 mpucapabilities; /* 0x94 */ 366 uint32 rom_reloc_addr; /* 0x98 */ 367 uint32 PAD[1]; 368 uint32 region_n_regs[16]; /* 0xa0 - 0xdc */ 369 uint32 PAD[16]; 370 uint32 initiat_n_masks[16]; /* 0x120 - 0x15c */ 371 uint32 PAD[32]; 372 uint32 clk_ctl_st; /* 0x1e0 */ 373 uint32 hw_war; /* 0x1e4 */ 374 uint32 powerctl; /* 0x1e8 */ 375 uint32 powerctl2; /* 0x1ec */ 376 } cr4regs_t; 377 #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg) 378 379 #define SBRESETLOG_CR4 0x4 380 381 /* cortex-A7 */ 382 typedef volatile struct { 383 uint32 corecontrol; /* 0x0 */ 384 uint32 corecapabilities; /* 0x4 */ 385 uint32 corestatus; /* 0x8 */ 386 uint32 tracecontrol; /* 0xc */ 387 uint32 gpioselect; /* 0x10 */ 388 uint32 gpioenable; /* 0x14 */ 389 uint32 PAD[114]; 390 uint32 clk_ctl_st; /* 0x1e0 */ 391 uint32 workaround; /* 0x1e4 */ 392 uint32 powerctl; /* 0x1e8 */ 393 uint32 powerctl2; /* 0x1ec */ 394 } ca7regs_t; 395 #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg) 396 397 #if defined(__ARM_ARCH_7M__) 398 #define ARMREG(regs, reg) ARM_CM3_REG(regs, reg) 399 #endif /* __ARM_ARCH_7M__ */ 400 401 #if defined(__ARM_ARCH_7R__) 402 #define ARMREG(regs, reg) ARM_CR4_REG(regs, reg) 403 #endif /* __ARM_ARCH_7R__ */ 404 405 #if defined(__ARM_ARCH_7A__) 406 #define ARMREG(regs, reg) ARM_CA7_REG(regs, reg) 407 #endif /* __ARM_ARCH_7A__ */ 408 409 /* MPU is present mask of ca7regs_t->corecapabilities */ 410 #define CAP_MPU_MASK 2000000u 411 412 #endif /* _LANGUAGE_ASSEMBLY */ 413 414 #endif /* _sbhndarm_h_ */ 415