1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ARM Cortex M3/M4/M7 SysTick timer driver
3*4882a593Smuzhiyun * (C) Copyright 2017 Renesas Electronics Europe Ltd
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on arch/arm/mach-stm32/stm32f1/timer.c
6*4882a593Smuzhiyun * (C) Copyright 2015
7*4882a593Smuzhiyun * Kamil Lulko, <kamil.lulko@gmail.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright 2015 ATS Advanced Telematics Systems GmbH
10*4882a593Smuzhiyun * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * The SysTick timer is a 24-bit count down timer. The clock can be either the
15*4882a593Smuzhiyun * CPU clock or a reference clock. Since the timer will wrap around very quickly
16*4882a593Smuzhiyun * when using the CPU clock, and we do not handle the timer interrupts, it is
17*4882a593Smuzhiyun * expected that this driver is only ever used with a slow reference clock.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * The number of reference clock ticks that correspond to 10ms is normally
20*4882a593Smuzhiyun * defined in the SysTick Calibration register's TENMS field. However, on some
21*4882a593Smuzhiyun * devices this is wrong, so this driver allows the clock rate to be defined
22*4882a593Smuzhiyun * using CONFIG_SYS_HZ_CLOCK.
23*4882a593Smuzhiyun */
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <common.h>
26*4882a593Smuzhiyun #include <asm/io.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */
31*4882a593Smuzhiyun #define SYSTICK_BASE 0xE000E010
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct cm3_systick {
34*4882a593Smuzhiyun uint32_t ctrl;
35*4882a593Smuzhiyun uint32_t reload_val;
36*4882a593Smuzhiyun uint32_t current_val;
37*4882a593Smuzhiyun uint32_t calibration;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define TIMER_MAX_VAL 0x00FFFFFF
41*4882a593Smuzhiyun #define SYSTICK_CTRL_EN BIT(0)
42*4882a593Smuzhiyun /* Clock source: 0 = Ref clock, 1 = CPU clock */
43*4882a593Smuzhiyun #define SYSTICK_CTRL_CPU_CLK BIT(2)
44*4882a593Smuzhiyun #define SYSTICK_CAL_NOREF BIT(31)
45*4882a593Smuzhiyun #define SYSTICK_CAL_SKEW BIT(30)
46*4882a593Smuzhiyun #define SYSTICK_CAL_TENMS_MASK 0x00FFFFFF
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* read the 24-bit timer */
read_timer(void)49*4882a593Smuzhiyun static ulong read_timer(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* The timer counts down, therefore convert to an incrementing timer */
54*4882a593Smuzhiyun return TIMER_MAX_VAL - readl(&systick->current_val);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
timer_init(void)57*4882a593Smuzhiyun int timer_init(void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct cm3_systick *systick = (struct cm3_systick *)SYSTICK_BASE;
60*4882a593Smuzhiyun u32 cal;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun writel(TIMER_MAX_VAL, &systick->reload_val);
63*4882a593Smuzhiyun /* Any write to current_val reg clears it to 0 */
64*4882a593Smuzhiyun writel(0, &systick->current_val);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun cal = readl(&systick->calibration);
67*4882a593Smuzhiyun if (cal & SYSTICK_CAL_NOREF)
68*4882a593Smuzhiyun /* Use CPU clock, no interrupts */
69*4882a593Smuzhiyun writel(SYSTICK_CTRL_EN | SYSTICK_CTRL_CPU_CLK, &systick->ctrl);
70*4882a593Smuzhiyun else
71*4882a593Smuzhiyun /* Use external clock, no interrupts */
72*4882a593Smuzhiyun writel(SYSTICK_CTRL_EN, &systick->ctrl);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /*
75*4882a593Smuzhiyun * If the TENMS field is inexact or wrong, specify the clock rate using
76*4882a593Smuzhiyun * CONFIG_SYS_HZ_CLOCK.
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun #if defined(CONFIG_SYS_HZ_CLOCK)
79*4882a593Smuzhiyun gd->arch.timer_rate_hz = CONFIG_SYS_HZ_CLOCK;
80*4882a593Smuzhiyun #else
81*4882a593Smuzhiyun gd->arch.timer_rate_hz = (cal & SYSTICK_CAL_TENMS_MASK) * 100;
82*4882a593Smuzhiyun #endif
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun gd->arch.tbl = 0;
85*4882a593Smuzhiyun gd->arch.tbu = 0;
86*4882a593Smuzhiyun gd->arch.lastinc = read_timer();
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun /* return milli-seconds timer value */
get_timer(ulong base)92*4882a593Smuzhiyun ulong get_timer(ulong base)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun unsigned long long t = get_ticks() * 1000;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return (ulong)((t / gd->arch.timer_rate_hz)) - base;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
get_ticks(void)99*4882a593Smuzhiyun unsigned long long get_ticks(void)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun u32 now = read_timer();
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (now >= gd->arch.lastinc)
104*4882a593Smuzhiyun gd->arch.tbl += (now - gd->arch.lastinc);
105*4882a593Smuzhiyun else
106*4882a593Smuzhiyun gd->arch.tbl += (TIMER_MAX_VAL - gd->arch.lastinc) + now;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun gd->arch.lastinc = now;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return gd->arch.tbl;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
get_tbclk(void)113*4882a593Smuzhiyun ulong get_tbclk(void)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return gd->arch.timer_rate_hz;
116*4882a593Smuzhiyun }
117