1 /* 2 * Broadcom SiliconBackplane ARM definitions 3 * 4 * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation 5 * 6 * Copyright (C) 1999-2017, Broadcom Corporation 7 * 8 * Unless you and Broadcom execute a separate written software license 9 * agreement governing use of this software, this software is licensed to you 10 * under the terms of the GNU General Public License version 2 (the "GPL"), 11 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 12 * following added to such license: 13 * 14 * As a special exception, the copyright holders of this software give you 15 * permission to link this software with independent modules, and to copy and 16 * distribute the resulting executable under terms of your choice, provided that 17 * you also meet, for each linked independent module, the terms and conditions of 18 * the license of that module. An independent module is a module which is not 19 * derived from this software. The special exception does not apply to any 20 * modifications of the software. 21 * 22 * Notwithstanding the above, under no circumstances may you combine this 23 * software in any way with any other Broadcom software provided under a license 24 * other than the GPL, without Broadcom's express prior written consent. 25 * 26 * 27 * <<Broadcom-WL-IPTag/Open:>> 28 * 29 * $Id: sbhndarm.h 699160 2017-05-12 04:50:25Z $ 30 */ 31 32 #ifndef _sbhndarm_h_ 33 #define _sbhndarm_h_ 34 35 #ifndef _LANGUAGE_ASSEMBLY 36 37 /* cpp contortions to concatenate w/arg prescan */ 38 #ifndef PAD 39 #define _PADLINE(line) pad ## line 40 #define _XSTR(line) _PADLINE(line) 41 #define PAD _XSTR(__LINE__) 42 #endif /* PAD */ 43 44 /* cortex-m3 */ 45 typedef volatile struct { 46 uint32 corecontrol; /* 0x0 */ 47 uint32 corestatus; /* 0x4 */ 48 uint32 PAD[1]; 49 uint32 biststatus; /* 0xc */ 50 uint32 nmiisrst; /* 0x10 */ 51 uint32 nmimask; /* 0x14 */ 52 uint32 isrmask; /* 0x18 */ 53 uint32 PAD[1]; 54 uint32 resetlog; /* 0x20 */ 55 uint32 gpioselect; /* 0x24 */ 56 uint32 gpioenable; /* 0x28 */ 57 uint32 PAD[1]; 58 uint32 bpaddrlo; /* 0x30 */ 59 uint32 bpaddrhi; /* 0x34 */ 60 uint32 bpdata; /* 0x38 */ 61 uint32 bpindaccess; /* 0x3c */ 62 uint32 ovlidx; /* 0x40 */ 63 uint32 ovlmatch; /* 0x44 */ 64 uint32 ovladdr; /* 0x48 */ 65 uint32 PAD[13]; 66 uint32 bwalloc; /* 0x80 */ 67 uint32 PAD[3]; 68 uint32 cyclecnt; /* 0x90 */ 69 uint32 inttimer; /* 0x94 */ 70 uint32 intmask; /* 0x98 */ 71 uint32 intstatus; /* 0x9c */ 72 uint32 PAD[80]; 73 uint32 clk_ctl_st; /* 0x1e0 */ 74 uint32 PAD[1]; 75 uint32 powerctl; /* 0x1e8 */ 76 } cm3regs_t; 77 #define ARM_CM3_REG(regs, reg) (&((cm3regs_t *)regs)->reg) 78 79 /* cortex-R4 */ 80 typedef volatile struct { 81 uint32 corecontrol; /* 0x0 */ 82 uint32 corecapabilities; /* 0x4 */ 83 uint32 corestatus; /* 0x8 */ 84 uint32 biststatus; /* 0xc */ 85 uint32 nmiisrst; /* 0x10 */ 86 uint32 nmimask; /* 0x14 */ 87 uint32 isrmask; /* 0x18 */ 88 uint32 swintreg; /* 0x1C */ 89 uint32 intstatus; /* 0x20 */ 90 uint32 intmask; /* 0x24 */ 91 uint32 cyclecnt; /* 0x28 */ 92 uint32 inttimer; /* 0x2c */ 93 uint32 gpioselect; /* 0x30 */ 94 uint32 gpioenable; /* 0x34 */ 95 uint32 PAD[2]; 96 uint32 bankidx; /* 0x40 */ 97 uint32 bankinfo; /* 0x44 */ 98 uint32 bankstbyctl; /* 0x48 */ 99 uint32 bankpda; /* 0x4c */ 100 uint32 PAD[6]; 101 uint32 tcampatchctrl; /* 0x68 */ 102 uint32 tcampatchtblbaseaddr; /* 0x6c */ 103 uint32 tcamcmdreg; /* 0x70 */ 104 uint32 tcamdatareg; /* 0x74 */ 105 uint32 tcambankxmaskreg; /* 0x78 */ 106 uint32 PAD[89]; 107 uint32 clk_ctl_st; /* 0x1e0 */ 108 uint32 PAD[1]; 109 uint32 powerctl; /* 0x1e8 */ 110 } cr4regs_t; 111 #define ARM_CR4_REG(regs, reg) (&((cr4regs_t *)regs)->reg) 112 113 /* cortex-A7 */ 114 typedef volatile struct { 115 uint32 corecontrol; /* 0x0 */ 116 uint32 corecapabilities; /* 0x4 */ 117 uint32 corestatus; /* 0x8 */ 118 uint32 tracecontrol; /* 0xc */ 119 uint32 PAD[8]; 120 uint32 gpioselect; /* 0x30 */ 121 uint32 gpioenable; /* 0x34 */ 122 uint32 PAD[106]; 123 uint32 clk_ctl_st; /* 0x1e0 */ 124 uint32 PAD[1]; 125 uint32 powerctl; /* 0x1e8 */ 126 } ca7regs_t; 127 #define ARM_CA7_REG(regs, reg) (&((ca7regs_t *)regs)->reg) 128 129 #if defined(__ARM_ARCH_7M__) 130 #define ARMREG(regs, reg) ARM_CM3_REG(regs, reg) 131 #endif /* __ARM_ARCH_7M__ */ 132 133 #if defined(__ARM_ARCH_7R__) 134 #define ARMREG(regs, reg) ARM_CR4_REG(regs, reg) 135 #endif /* __ARM_ARCH_7R__ */ 136 137 #if defined(__ARM_ARCH_7A__) 138 #define ARMREG(regs, reg) ARM_CA7_REG(regs, reg) 139 #endif /* __ARM_ARCH_7A__ */ 140 141 #endif /* _LANGUAGE_ASSEMBLY */ 142 143 #endif /* _sbhndarm_h_ */ 144