1 /* 2 * Broadcom HND chip & on-chip-interconnect-related definitions. 3 * 4 * Copyright (C) 2020, Broadcom. 5 * 6 * Unless you and Broadcom execute a separate written software license 7 * agreement governing use of this software, this software is licensed to you 8 * under the terms of the GNU General Public License version 2 (the "GPL"), 9 * available at http://www.broadcom.com/licenses/GPLv2.php, with the 10 * following added to such license: 11 * 12 * As a special exception, the copyright holders of this software give you 13 * permission to link this software with independent modules, and to copy and 14 * distribute the resulting executable under terms of your choice, provided that 15 * you also meet, for each linked independent module, the terms and conditions of 16 * the license of that module. An independent module is a module which is not 17 * derived from this software. The special exception does not apply to any 18 * modifications of the software. 19 * 20 * 21 * <<Broadcom-WL-IPTag/Dual:>> 22 */ 23 24 #ifndef _HNDSOC_H 25 #define _HNDSOC_H 26 27 /* Include the soci specific files */ 28 #include <sbconfig.h> 29 #include <aidmp.h> 30 31 /* 32 * SOC Interconnect Address Map. 33 * All regions may not exist on all chips. 34 */ 35 #define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */ 36 #define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 37 #define SI_PCI_MEM_SZ (64 * 1024 * 1024) 38 #define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 39 #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ 40 #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ 41 42 #ifndef SI_ENUM_BASE_DEFAULT 43 #define SI_ENUM_BASE_DEFAULT 0x18000000 /* Enumeration space base */ 44 #endif 45 46 #ifndef SI_WRAP_BASE_DEFAULT 47 #define SI_WRAP_BASE_DEFAULT 0x18100000 /* Wrapper space base */ 48 #endif 49 50 #define WL_BRIDGE1_S (0x18132000) 51 #define WL_BRIDGE2_S (0x18133000) 52 53 /** new(er) chips started locating their chipc core at a different BP address than 0x1800_0000 */ 54 #ifdef DONGLEBUILD 55 // firmware is always compiled for a particular chip 56 #define SI_ENUM_BASE(sih) SI_ENUM_BASE_DEFAULT 57 #define SI_WRAP_BASE(sih) SI_WRAP_BASE_DEFAULT 58 #else 59 // NIC and DHD driver binaries should support both old(er) and new(er) chips at the same time 60 #define SI_ENUM_BASE(sih) ((sih)->enum_base) 61 #define SI_WRAP_BASE(sih) (SI_ENUM_BASE(sih) + 0x00100000) 62 #endif /* DONGLEBUILD */ 63 64 #define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ 65 66 #define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */ 67 #define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */ 68 #define SI_GPV_RD_CAP_EN 0x1 /* issue read */ 69 #define SI_GPV_WR_CAP_EN 0x2 /* issue write */ 70 71 #define SI_GPV_SL4_BM_ADDR 0x44024 /* NIC-400 Slave interface 4 Bypass merge */ 72 #define SI_GPV_SL6_BM_ADDR 0x46024 /* NIC-400 Slave interface 6 Bypass merge */ 73 #define SI_GPV_SL8_BM_ADDR 0x4a024 /* NIC-400 Slave interface 8 Bypass merge */ 74 #define SI_GPV_SL9_BM_ADDR 0x4b024 /* NIC-400 Slave interface 9 Bypass merge */ 75 76 /* AXI Slave Interface Block (ASIB) offsets */ 77 #define ASIB_FN_MOD2 0x24 78 79 #ifndef SI_MAXCORES 80 #ifdef _RTE_ 81 #define SI_MAXCORES 16 /* Max cores (this is arbitrary, for software 82 * convenience and could be changed if we 83 * make any larger chips 84 */ 85 #else 86 #define SI_MAXCORES 32 /* NorthStar has more cores */ 87 #endif /* _RTE_ */ 88 #endif /* SI_MAXCORES */ 89 90 #define SI_MAXBR 4 /* Max bridges (this is arbitrary, for software 91 * convenience and could be changed if we 92 * make any larger chips 93 */ 94 95 #define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */ 96 #define SI_FASTRAM_SWAPPED 0x19800000 97 98 #define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */ 99 #define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */ 100 #define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */ 101 #define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */ 102 #define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */ 103 #define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */ 104 105 #define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */ 106 #define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */ 107 #define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */ 108 #define SI_NS_FLASH_WINDOW 0x02000000 /* Flash XIP Window */ 109 110 #define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */ 111 #define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */ 112 #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ 113 #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ 114 #define SI_ARMCA7_ROM 0x00000000 /* ARM Cortex-A7 ROM */ 115 #ifndef SI_ARMCA7_RAM 116 #define SI_ARMCA7_RAM 0x00200000 /* ARM Cortex-A7 RAM */ 117 #endif 118 #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ 119 #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ 120 121 #define SI_SFLASH 0x14000000 122 #define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 123 #define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */ 124 #define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */ 125 #define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 126 * (2 ZettaBytes), low 32 bits 127 */ 128 #define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 129 * (2 ZettaBytes), high 32 bits 130 */ 131 132 /* APB bridge code */ 133 #define APB_BRIDGE_ID 0x135 /* APB Bridge 0, 1, etc. */ 134 135 /* ADB bridge code */ 136 #define ADB_BRIDGE_ID 0x031 137 138 /* AXI-AHB bridge code */ 139 #define AXI2AHB_BRIDGE_ID 0x240 /* AXI_AHB Bridge */ 140 141 /* core codes */ 142 #define NODEV_CORE_ID 0x700 /* Invalid coreid */ 143 #define CC_CORE_ID 0x800 /* chipcommon core */ 144 #define ILINE20_CORE_ID 0x801 /* iline20 core */ 145 #define SRAM_CORE_ID 0x802 /* sram core */ 146 #define SDRAM_CORE_ID 0x803 /* sdram core */ 147 #define PCI_CORE_ID 0x804 /* pci core */ 148 #define MIPS_CORE_ID 0x805 /* mips core */ 149 #define ENET_CORE_ID 0x806 /* enet mac core */ 150 #define CODEC_CORE_ID 0x807 /* v90 codec core */ 151 #define USB_CORE_ID 0x808 /* usb 1.1 host/device core */ 152 #define ADSL_CORE_ID 0x809 /* ADSL core */ 153 #define ILINE100_CORE_ID 0x80a /* iline100 core */ 154 #define IPSEC_CORE_ID 0x80b /* ipsec core */ 155 #define UTOPIA_CORE_ID 0x80c /* utopia core */ 156 #define PCMCIA_CORE_ID 0x80d /* pcmcia core */ 157 #define SOCRAM_CORE_ID 0x80e /* internal memory core */ 158 #define MEMC_CORE_ID 0x80f /* memc sdram core */ 159 #define OFDM_CORE_ID 0x810 /* OFDM phy core */ 160 #define EXTIF_CORE_ID 0x811 /* external interface core */ 161 #define D11_CORE_ID 0x812 /* 802.11 MAC core */ 162 #define APHY_CORE_ID 0x813 /* 802.11a phy core */ 163 #define BPHY_CORE_ID 0x814 /* 802.11b phy core */ 164 #define GPHY_CORE_ID 0x815 /* 802.11g phy core */ 165 #define MIPS33_CORE_ID 0x816 /* mips3302 core */ 166 #define USB11H_CORE_ID 0x817 /* usb 1.1 host core */ 167 #define USB11D_CORE_ID 0x818 /* usb 1.1 device core */ 168 #define USB20H_CORE_ID 0x819 /* usb 2.0 host core */ 169 #define USB20D_CORE_ID 0x81a /* usb 2.0 device core */ 170 #define SDIOH_CORE_ID 0x81b /* sdio host core */ 171 #define ROBO_CORE_ID 0x81c /* roboswitch core */ 172 #define ATA100_CORE_ID 0x81d /* parallel ATA core */ 173 #define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */ 174 #define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */ 175 #define PCIE_CORE_ID 0x820 /* pci express core */ 176 #define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */ 177 #define SRAMC_CORE_ID 0x822 /* SRAM controller core */ 178 #define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */ 179 #define ARM11_CORE_ID 0x824 /* ARM 1176 core */ 180 #define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */ 181 #define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */ 182 #define PMU_CORE_ID 0x827 /* PMU core */ 183 #define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */ 184 #define SDIOD_CORE_ID 0x829 /* SDIO device core */ 185 #define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */ 186 #define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */ 187 #define MIPS74K_CORE_ID 0x82c /* mips 74k core */ 188 #define GMAC_CORE_ID 0x82d /* Gigabit MAC core */ 189 #define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */ 190 #define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */ 191 #define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */ 192 #define SC_CORE_ID 0x831 /* shared common core */ 193 #define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */ 194 #define SPIH_CORE_ID 0x833 /* SPI host core */ 195 #define I2S_CORE_ID 0x834 /* I2S core */ 196 #define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */ 197 #define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */ 198 199 #define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */ 200 #define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */ 201 #define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ 202 #define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ 203 #define GCI_CORE_ID 0x840 /* GCI Core */ 204 #define SR_CORE_ID 0x841 /* SR_CORE ID */ 205 #define M2MDMA_CORE_ID 0x844 /* memory to memory dma */ 206 #define CMEM_CORE_ID 0x846 /* CNDS DDR2/3 memory controller */ 207 #define ARMCA7_CORE_ID 0x847 /* ARM CA7 CPU */ 208 #define SYSMEM_CORE_ID 0x849 /* System memory core */ 209 #define HUB_CORE_ID 0x84b /* Hub core ID */ 210 #define HWA_CORE_ID 0x851 /* HWA Core ID */ 211 #define SPMI_SLAVE_CORE_ID 0x855 /* SPMI Slave Core ID */ 212 #define BT_CORE_ID 0x857 /* Bluetooth Core ID */ 213 #define HND_OOBR_CORE_ID 0x85c /* Hnd oob router core ID */ 214 #define SOE_CORE_ID 0x85d /* SOE core */ 215 #define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ 216 #define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ 217 #define EROM_CORE_ID 0x366 /* EROM core ID */ 218 #define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */ 219 #define CCI400_CORE_ID 0x420 /* CCI-400 (Cache Coherent Interconnect) core ID */ 220 #define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all 221 * unused address ranges 222 */ 223 224 #define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */ 225 #define NS_DMA_CORE_ID 0x502 /* DMA core */ 226 #define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */ 227 #define NS_USB20_CORE_ID 0x504 /* USB2.0 core */ 228 #define NS_USB30_CORE_ID 0x505 /* USB3.0 core */ 229 #define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */ 230 #define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */ 231 #define NS_ROM_CORE_ID 0x508 /* ROM core */ 232 #define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */ 233 #define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */ 234 #define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */ 235 #define NS_SOCRAM_CORE_ID 0x50e /* internal memory core */ 236 #define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */ 237 #define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */ 238 #define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ 239 #define ALTA_CORE_ID 0x534 /* I2S core */ 240 #define DDR23_PHY_CORE_ID 0x5dd 241 242 #define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */ 243 #define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */ 244 #define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2 245 * (2 ZettaBytes), high 32 bits 246 */ 247 #define NS_PCIEG2_CORE_REV_B0 0x7 /* NS-B0 PCIE Gen 2 core rev */ 248 249 /* There are TWO constants on all HND chips: SI_ENUM_BASE_DEFAULT above, 250 * and chipcommon being the first core: 251 */ 252 #define SI_CC_IDX 0 253 /* SOC Interconnect types (aka chip types) */ 254 #define SOCI_SB 0u 255 #define SOCI_AI 1u 256 #define SOCI_UBUS 2u 257 #define SOCI_NAI 3u 258 #define SOCI_DVTBUS 4u /* BCM7XXX Digital Video Tech bus */ 259 #define SOCI_NCI 6u /* NCI (non coherent interconnect) i.e. BOOKER */ 260 261 /* Common core control flags */ 262 #define SICF_BIST_EN 0x8000 263 #define SICF_PME_EN 0x4000 264 #define SICF_CORE_BITS 0x3ffc 265 #define SICF_PCEN 0x0004 266 #define SICF_FGC 0x0002 267 #define SICF_CLOCK_EN 0x0001 268 269 /* Common core status flags */ 270 #define SISF_BIST_DONE 0x8000 271 #define SISF_BIST_ERROR 0x4000 272 #define SISF_GATED_CLK 0x2000 273 #define SISF_DMA64 0x1000 274 #define SISF_CORE_BITS 0x0fff 275 #define SISF_CORE_BITS_SCAN 0x0010 /* SCAN core */ 276 277 /* Norstar core status flags */ 278 #define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */ 279 #define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */ 280 #define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */ 281 #define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */ 282 #define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */ 283 #define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */ 284 285 /* dot11 core-specific status flags */ 286 #define SISF_MINORREV_D11_SHIFT 16 287 #define SISF_MINORREV_D11_MASK 0xF /**< minor corerev (corerev == 61) */ 288 289 /* A register that is common to all cores to 290 * communicate w/PMU regarding clock control. 291 */ 292 #define SI_CLK_CTL_ST 0x1e0 /* clock control and status */ 293 #define SI_PWR_CTL_ST 0x1e8 /* For memory clock gating */ 294 295 /* clk_ctl_st register */ 296 #define CCS_FORCEALP 0x00000001 /* force ALP request */ 297 #define CCS_FORCEHT 0x00000002 /* force HT request */ 298 #define CCS_FORCEILP 0x00000004 /* force ILP request */ 299 #define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */ 300 #define CCS_HTAREQ 0x00000010 /* HT Avail Request */ 301 #define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */ 302 #define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */ 303 #define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ 304 #define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */ 305 #define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4/CA7 fast clock request */ 306 #define CCS_SFLASH_CLKREQ 0x00000200 /* Sflash clk request */ 307 #define CCS_AVBCLKREQ 0x00000400 /* AVB Clock enable request */ 308 #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ 309 #define CCS_ERSRC_REQ_SHIFT 8 310 #define CCS_ALPAVAIL 0x00010000 /* ALP is available */ 311 #define CCS_HTAVAIL 0x00020000 /* HT is available */ 312 #define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */ 313 #define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */ 314 #define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */ 315 #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ 316 #define CCS_ERSRC_STS_SHIFT 24 317 #define CCS_SECI_AVAIL 0x01000000 /* RO: SECI is available */ 318 319 /* Not really related to SOC Interconnect, but a couple of software 320 * conventions for the use the flash space: 321 */ 322 323 /* Minumum amount of flash we support */ 324 #define FLASH_MIN 0x00020000 /* Minimum flash size */ 325 326 /* A boot/binary may have an embedded block that describes its size */ 327 #define BISZ_OFFSET 0x3e0 /* At this offset into the binary */ 328 #define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */ 329 #define BISZ_MAGIC_IDX 0 /* Word 0: magic */ 330 #define BISZ_TXTST_IDX 1 /* 1: text start */ 331 #define BISZ_TXTEND_IDX 2 /* 2: text end */ 332 #define BISZ_DATAST_IDX 3 /* 3: data start */ 333 #define BISZ_DATAEND_IDX 4 /* 4: data end */ 334 #define BISZ_BSSST_IDX 5 /* 5: bss start */ 335 #define BISZ_BSSEND_IDX 6 /* 6: bss end */ 336 #define BISZ_SIZE 7 /* descriptor size in 32-bit integers */ 337 338 /* Boot/Kernel related defintion and functions */ 339 #define SOC_BOOTDEV_ROM 0x00000001 340 #define SOC_BOOTDEV_PFLASH 0x00000002 341 #define SOC_BOOTDEV_SFLASH 0x00000004 342 #define SOC_BOOTDEV_NANDFLASH 0x00000008 343 344 #define SOC_KNLDEV_NORFLASH 0x00000002 345 #define SOC_KNLDEV_NANDFLASH 0x00000004 346 347 #if !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) 348 int soc_boot_dev(void *sih); 349 int soc_knl_dev(void *sih); 350 #endif /* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */ 351 352 #define PMU_BASE_OFFSET 0x00012000 /* PMU offset is changed for ccrev >= 56 */ 353 #endif /* _HNDSOC_H */ 354