1# arm cpu features 2config BR2_ARM_CPU_HAS_NEON 3 bool 4 5# for some cores, NEON support is optional 6config BR2_ARM_CPU_MAYBE_HAS_NEON 7 bool 8 9# For some cores, the FPU is optional 10config BR2_ARM_CPU_MAYBE_HAS_FPU 11 bool 12 13config BR2_ARM_CPU_HAS_FPU 14 bool 15 16# for some cores, VFPv2 is optional 17config BR2_ARM_CPU_MAYBE_HAS_VFPV2 18 bool 19 select BR2_ARM_CPU_MAYBE_HAS_FPU 20 21config BR2_ARM_CPU_HAS_VFPV2 22 bool 23 select BR2_ARM_CPU_HAS_FPU 24 25# for some cores, VFPv3 is optional 26config BR2_ARM_CPU_MAYBE_HAS_VFPV3 27 bool 28 select BR2_ARM_CPU_MAYBE_HAS_VFPV2 29 30config BR2_ARM_CPU_HAS_VFPV3 31 bool 32 select BR2_ARM_CPU_HAS_VFPV2 33 34# for some cores, VFPv4 is optional 35config BR2_ARM_CPU_MAYBE_HAS_VFPV4 36 bool 37 select BR2_ARM_CPU_MAYBE_HAS_VFPV3 38 39config BR2_ARM_CPU_HAS_VFPV4 40 bool 41 select BR2_ARM_CPU_HAS_VFPV3 42 43# FPv4 is always optional 44config BR2_ARM_CPU_MAYBE_HAS_FPV4 45 bool 46 select BR2_ARM_CPU_MAYBE_HAS_FPU 47 48config BR2_ARM_CPU_HAS_FPV4 49 bool 50 select BR2_ARM_CPU_HAS_FPU 51 52# FPv5 is always optional 53config BR2_ARM_CPU_MAYBE_HAS_FPV5 54 bool 55 select BR2_ARM_CPU_MAYBE_HAS_FPV4 56 57config BR2_ARM_CPU_HAS_FPV5 58 bool 59 select BR2_ARM_CPU_HAS_FPV4 60 61config BR2_ARM_CPU_HAS_FP_ARMV8 62 bool 63 select BR2_ARM_CPU_HAS_VFPV4 64 65config BR2_ARM_CPU_HAS_ARM 66 bool 67 68config BR2_ARM_CPU_HAS_THUMB 69 bool 70 71config BR2_ARM_CPU_HAS_THUMB2 72 bool 73 74config BR2_ARM_CPU_ARMV4 75 bool 76 77config BR2_ARM_CPU_ARMV5 78 bool 79 80config BR2_ARM_CPU_ARMV6 81 bool 82 83config BR2_ARM_CPU_ARMV7A 84 bool 85 86config BR2_ARM_CPU_ARMV7M 87 bool 88 89config BR2_ARM_CPU_ARMV8A 90 bool 91 92choice 93 prompt "Target Architecture Variant" 94 default BR2_cortex_a53 if BR2_ARCH_IS_64 95 default BR2_arm926t 96 help 97 Specific CPU variant to use 98 99if !BR2_ARCH_IS_64 100comment "armv4 cores" 101config BR2_arm920t 102 bool "arm920t" 103 select BR2_ARM_CPU_HAS_ARM 104 select BR2_ARM_CPU_HAS_THUMB 105 select BR2_ARM_CPU_ARMV4 106 select BR2_ARCH_HAS_MMU_OPTIONAL 107config BR2_arm922t 108 bool "arm922t" 109 select BR2_ARM_CPU_HAS_ARM 110 select BR2_ARM_CPU_HAS_THUMB 111 select BR2_ARM_CPU_ARMV4 112 select BR2_ARCH_HAS_MMU_OPTIONAL 113config BR2_fa526 114 bool "fa526/626" 115 select BR2_ARM_CPU_HAS_ARM 116 select BR2_ARM_CPU_ARMV4 117 select BR2_ARCH_HAS_MMU_OPTIONAL 118config BR2_strongarm 119 bool "strongarm sa110/sa1100" 120 select BR2_ARM_CPU_HAS_ARM 121 select BR2_ARM_CPU_ARMV4 122 select BR2_ARCH_HAS_MMU_OPTIONAL 123 124comment "armv5 cores" 125config BR2_arm926t 126 bool "arm926t" 127 select BR2_ARM_CPU_HAS_ARM 128 select BR2_ARM_CPU_MAYBE_HAS_VFPV2 129 select BR2_ARM_CPU_HAS_THUMB 130 select BR2_ARM_CPU_ARMV5 131 select BR2_ARCH_HAS_MMU_OPTIONAL 132config BR2_iwmmxt 133 bool "iwmmxt" 134 select BR2_ARM_CPU_HAS_ARM 135 select BR2_ARM_CPU_ARMV5 136 select BR2_ARCH_HAS_MMU_OPTIONAL 137config BR2_xscale 138 bool "xscale" 139 select BR2_ARM_CPU_HAS_ARM 140 select BR2_ARM_CPU_HAS_THUMB 141 select BR2_ARM_CPU_ARMV5 142 select BR2_ARCH_HAS_MMU_OPTIONAL 143 144comment "armv6 cores" 145config BR2_arm1136j_s 146 bool "arm1136j-s" 147 select BR2_ARM_CPU_HAS_ARM 148 select BR2_ARM_CPU_HAS_THUMB 149 select BR2_ARM_CPU_ARMV6 150 select BR2_ARCH_HAS_MMU_OPTIONAL 151config BR2_arm1136jf_s 152 bool "arm1136jf-s" 153 select BR2_ARM_CPU_HAS_ARM 154 select BR2_ARM_CPU_HAS_VFPV2 155 select BR2_ARM_CPU_HAS_THUMB 156 select BR2_ARM_CPU_ARMV6 157 select BR2_ARCH_HAS_MMU_OPTIONAL 158config BR2_arm1176jz_s 159 bool "arm1176jz-s" 160 select BR2_ARM_CPU_HAS_ARM 161 select BR2_ARM_CPU_HAS_THUMB 162 select BR2_ARM_CPU_ARMV6 163 select BR2_ARCH_HAS_MMU_OPTIONAL 164config BR2_arm1176jzf_s 165 bool "arm1176jzf-s" 166 select BR2_ARM_CPU_HAS_ARM 167 select BR2_ARM_CPU_HAS_VFPV2 168 select BR2_ARM_CPU_HAS_THUMB 169 select BR2_ARM_CPU_ARMV6 170 select BR2_ARCH_HAS_MMU_OPTIONAL 171config BR2_arm11mpcore 172 bool "mpcore" 173 select BR2_ARM_CPU_HAS_ARM 174 select BR2_ARM_CPU_MAYBE_HAS_VFPV2 175 select BR2_ARM_CPU_HAS_THUMB 176 select BR2_ARM_CPU_ARMV6 177 select BR2_ARCH_HAS_MMU_OPTIONAL 178 179comment "armv7a cores" 180config BR2_cortex_a5 181 bool "cortex-A5" 182 select BR2_ARM_CPU_HAS_ARM 183 select BR2_ARM_CPU_MAYBE_HAS_NEON 184 select BR2_ARM_CPU_MAYBE_HAS_VFPV4 185 select BR2_ARM_CPU_HAS_THUMB2 186 select BR2_ARM_CPU_ARMV7A 187 select BR2_ARCH_HAS_MMU_OPTIONAL 188config BR2_cortex_a7 189 bool "cortex-A7" 190 select BR2_ARM_CPU_HAS_ARM 191 select BR2_ARM_CPU_HAS_NEON 192 select BR2_ARM_CPU_HAS_VFPV4 193 select BR2_ARM_CPU_HAS_THUMB2 194 select BR2_ARM_CPU_ARMV7A 195 select BR2_ARCH_HAS_MMU_OPTIONAL 196config BR2_cortex_a8 197 bool "cortex-A8" 198 select BR2_ARM_CPU_HAS_ARM 199 select BR2_ARM_CPU_HAS_NEON 200 select BR2_ARM_CPU_HAS_VFPV3 201 select BR2_ARM_CPU_HAS_THUMB2 202 select BR2_ARM_CPU_ARMV7A 203 select BR2_ARCH_HAS_MMU_OPTIONAL 204config BR2_cortex_a9 205 bool "cortex-A9" 206 select BR2_ARM_CPU_HAS_ARM 207 select BR2_ARM_CPU_MAYBE_HAS_NEON 208 select BR2_ARM_CPU_MAYBE_HAS_VFPV3 209 select BR2_ARM_CPU_HAS_THUMB2 210 select BR2_ARM_CPU_ARMV7A 211 select BR2_ARCH_HAS_MMU_OPTIONAL 212config BR2_cortex_a12 213 bool "cortex-A12" 214 select BR2_ARM_CPU_HAS_ARM 215 select BR2_ARM_CPU_HAS_NEON 216 select BR2_ARM_CPU_HAS_VFPV4 217 select BR2_ARM_CPU_HAS_THUMB2 218 select BR2_ARM_CPU_ARMV7A 219 select BR2_ARCH_HAS_MMU_OPTIONAL 220config BR2_cortex_a15 221 bool "cortex-A15" 222 select BR2_ARM_CPU_HAS_ARM 223 select BR2_ARM_CPU_HAS_NEON 224 select BR2_ARM_CPU_HAS_VFPV4 225 select BR2_ARM_CPU_HAS_THUMB2 226 select BR2_ARM_CPU_ARMV7A 227 select BR2_ARCH_HAS_MMU_OPTIONAL 228config BR2_cortex_a15_a7 229 bool "cortex-A15/A7 big.LITTLE" 230 select BR2_ARM_CPU_HAS_ARM 231 select BR2_ARM_CPU_HAS_NEON 232 select BR2_ARM_CPU_HAS_VFPV4 233 select BR2_ARM_CPU_HAS_THUMB2 234 select BR2_ARM_CPU_ARMV7A 235 select BR2_ARCH_HAS_MMU_OPTIONAL 236 select BR2_ARCH_NEEDS_GCC_AT_LEAST_4_9 237config BR2_cortex_a17 238 bool "cortex-A17" 239 select BR2_ARM_CPU_HAS_ARM 240 select BR2_ARM_CPU_HAS_NEON 241 select BR2_ARM_CPU_HAS_VFPV4 242 select BR2_ARM_CPU_HAS_THUMB2 243 select BR2_ARM_CPU_ARMV7A 244 select BR2_ARCH_HAS_MMU_OPTIONAL 245 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 246config BR2_cortex_a17_a7 247 bool "cortex-A17/A7 big.LITTLE" 248 select BR2_ARM_CPU_HAS_ARM 249 select BR2_ARM_CPU_HAS_NEON 250 select BR2_ARM_CPU_HAS_VFPV4 251 select BR2_ARM_CPU_HAS_THUMB2 252 select BR2_ARM_CPU_ARMV7A 253 select BR2_ARCH_HAS_MMU_OPTIONAL 254 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 255config BR2_pj4 256 bool "pj4" 257 select BR2_ARM_CPU_HAS_ARM 258 select BR2_ARM_CPU_HAS_VFPV3 259 select BR2_ARM_CPU_ARMV7A 260 select BR2_ARCH_HAS_MMU_OPTIONAL 261 262comment "armv7m cores" 263config BR2_cortex_m3 264 bool "cortex-M3" 265 select BR2_ARM_CPU_HAS_THUMB2 266 select BR2_ARM_CPU_ARMV7M 267config BR2_cortex_m4 268 bool "cortex-M4" 269 select BR2_ARM_CPU_HAS_THUMB2 270 select BR2_ARM_CPU_MAYBE_HAS_FPV4 271 select BR2_ARM_CPU_ARMV7M 272config BR2_cortex_m7 273 bool "cortex-M7" 274 select BR2_ARM_CPU_HAS_THUMB2 275 select BR2_ARM_CPU_MAYBE_HAS_FPV5 276 select BR2_ARM_CPU_ARMV7M 277 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 278endif # !BR2_ARCH_IS_64 279 280comment "armv8 cores" 281config BR2_cortex_a32 282 bool "cortex-A32" 283 depends on !BR2_ARCH_IS_64 284 select BR2_ARM_CPU_HAS_ARM 285 select BR2_ARM_CPU_HAS_NEON 286 select BR2_ARM_CPU_HAS_THUMB2 287 select BR2_ARM_CPU_HAS_FP_ARMV8 288 select BR2_ARM_CPU_ARMV8A 289 select BR2_ARCH_HAS_MMU_OPTIONAL 290 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 291config BR2_cortex_a35 292 bool "cortex-A35" 293 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 294 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 295 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 296 select BR2_ARM_CPU_HAS_FP_ARMV8 297 select BR2_ARM_CPU_ARMV8A 298 select BR2_ARCH_HAS_MMU_OPTIONAL 299 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 300config BR2_cortex_a53 301 bool "cortex-A53" 302 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 303 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 304 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 305 select BR2_ARM_CPU_HAS_FP_ARMV8 306 select BR2_ARM_CPU_ARMV8A 307 select BR2_ARCH_HAS_MMU_OPTIONAL 308config BR2_cortex_a57 309 bool "cortex-A57" 310 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 311 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 312 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 313 select BR2_ARM_CPU_HAS_FP_ARMV8 314 select BR2_ARM_CPU_ARMV8A 315 select BR2_ARCH_HAS_MMU_OPTIONAL 316config BR2_cortex_a57_a53 317 bool "cortex-A57/A53 big.LITTLE" 318 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 319 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 320 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 321 select BR2_ARM_CPU_HAS_FP_ARMV8 322 select BR2_ARM_CPU_ARMV8A 323 select BR2_ARCH_HAS_MMU_OPTIONAL 324 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 325config BR2_cortex_a72 326 bool "cortex-A72" 327 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 328 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 329 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 330 select BR2_ARM_CPU_HAS_FP_ARMV8 331 select BR2_ARM_CPU_ARMV8A 332 select BR2_ARCH_HAS_MMU_OPTIONAL 333 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 334config BR2_cortex_a72_a53 335 bool "cortex-A72/A53 big.LITTLE" 336 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 337 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 338 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 339 select BR2_ARM_CPU_HAS_FP_ARMV8 340 select BR2_ARM_CPU_ARMV8A 341 select BR2_ARCH_HAS_MMU_OPTIONAL 342 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 343config BR2_cortex_a73 344 bool "cortex-A73" 345 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 346 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 347 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 348 select BR2_ARM_CPU_HAS_FP_ARMV8 349 select BR2_ARM_CPU_ARMV8A 350 select BR2_ARCH_HAS_MMU_OPTIONAL 351 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 352config BR2_cortex_a73_a35 353 bool "cortex-A73/A35 big.LITTLE" 354 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 355 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 356 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 357 select BR2_ARM_CPU_HAS_FP_ARMV8 358 select BR2_ARM_CPU_ARMV8A 359 select BR2_ARCH_HAS_MMU_OPTIONAL 360 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 361config BR2_cortex_a73_a53 362 bool "cortex-A73/A53 big.LITTLE" 363 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 364 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 365 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 366 select BR2_ARM_CPU_HAS_FP_ARMV8 367 select BR2_ARM_CPU_ARMV8A 368 select BR2_ARCH_HAS_MMU_OPTIONAL 369 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 370config BR2_emag 371 bool "emag" 372 depends on BR2_ARCH_IS_64 373 select BR2_ARM_CPU_HAS_FP_ARMV8 374 select BR2_ARM_CPU_ARMV8A 375 select BR2_ARCH_HAS_MMU_OPTIONAL 376 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 377config BR2_exynos_m1 378 bool "exynos-m1" 379 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 380 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 381 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 382 select BR2_ARM_CPU_HAS_FP_ARMV8 383 select BR2_ARM_CPU_ARMV8A 384 select BR2_ARCH_HAS_MMU_OPTIONAL 385 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 386config BR2_falkor 387 bool "falkor" 388 depends on BR2_ARCH_IS_64 389 select BR2_ARM_CPU_HAS_FP_ARMV8 390 select BR2_ARM_CPU_ARMV8A 391 select BR2_ARCH_HAS_MMU_OPTIONAL 392 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 393config BR2_phecda 394 bool "phecda" 395 depends on BR2_ARCH_IS_64 396 select BR2_ARM_CPU_HAS_FP_ARMV8 397 select BR2_ARM_CPU_ARMV8A 398 select BR2_ARCH_HAS_MMU_OPTIONAL 399 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 400config BR2_qdf24xx 401 bool "qdf24xx" 402 depends on BR2_ARCH_IS_64 403 select BR2_ARM_CPU_HAS_FP_ARMV8 404 select BR2_ARM_CPU_ARMV8A 405 select BR2_ARCH_HAS_MMU_OPTIONAL 406 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 407config BR2_thunderx 408 bool "thunderx (aka octeontx)" 409 depends on BR2_ARCH_IS_64 410 select BR2_ARM_CPU_HAS_FP_ARMV8 411 select BR2_ARM_CPU_ARMV8A 412 select BR2_ARCH_HAS_MMU_OPTIONAL 413 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 414config BR2_thunderxt81 415 bool "thunderxt81 (aka octeontx81)" 416 depends on BR2_ARCH_IS_64 417 select BR2_ARM_CPU_HAS_FP_ARMV8 418 select BR2_ARM_CPU_ARMV8A 419 select BR2_ARCH_HAS_MMU_OPTIONAL 420 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 421config BR2_thunderxt83 422 bool "thunderxt83 (aka octeontx83)" 423 depends on BR2_ARCH_IS_64 424 select BR2_ARM_CPU_HAS_FP_ARMV8 425 select BR2_ARM_CPU_ARMV8A 426 select BR2_ARCH_HAS_MMU_OPTIONAL 427 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 428config BR2_thunderxt88 429 bool "thunderxt88" 430 depends on BR2_ARCH_IS_64 431 select BR2_ARM_CPU_HAS_FP_ARMV8 432 select BR2_ARM_CPU_ARMV8A 433 select BR2_ARCH_HAS_MMU_OPTIONAL 434 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 435config BR2_thunderxt88p1 436 bool "thunderxt88p1" 437 depends on BR2_ARCH_IS_64 438 select BR2_ARM_CPU_HAS_FP_ARMV8 439 select BR2_ARM_CPU_ARMV8A 440 select BR2_ARCH_HAS_MMU_OPTIONAL 441 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 442config BR2_xgene1 443 bool "xgene1" 444 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 445 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 446 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 447 select BR2_ARM_CPU_HAS_FP_ARMV8 448 select BR2_ARM_CPU_ARMV8A 449 select BR2_ARCH_HAS_MMU_OPTIONAL 450 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 451 452comment "armv8.1a cores" 453config BR2_thunderx2t99 454 bool "thunderx2t99" 455 depends on BR2_ARCH_IS_64 456 select BR2_ARM_CPU_HAS_FP_ARMV8 457 select BR2_ARM_CPU_ARMV8A 458 select BR2_ARCH_HAS_MMU_OPTIONAL 459 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 460config BR2_thunderx2t99p1 461 bool "thunderx2t99p1" 462 depends on BR2_ARCH_IS_64 463 select BR2_ARM_CPU_HAS_FP_ARMV8 464 select BR2_ARM_CPU_ARMV8A 465 select BR2_ARCH_HAS_MMU_OPTIONAL 466 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 467config BR2_vulcan 468 bool "vulcan" 469 depends on BR2_ARCH_IS_64 470 select BR2_ARM_CPU_HAS_FP_ARMV8 471 select BR2_ARM_CPU_ARMV8A 472 select BR2_ARCH_HAS_MMU_OPTIONAL 473 select BR2_ARCH_NEEDS_GCC_AT_LEAST_7 474 475comment "armv8.2a cores" 476config BR2_cortex_a55 477 bool "cortex-A55" 478 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 479 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 480 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 481 select BR2_ARM_CPU_HAS_FP_ARMV8 482 select BR2_ARM_CPU_ARMV8A 483 select BR2_ARCH_HAS_MMU_OPTIONAL 484 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 485config BR2_cortex_a75 486 bool "cortex-A75" 487 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 488 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 489 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 490 select BR2_ARM_CPU_HAS_FP_ARMV8 491 select BR2_ARM_CPU_ARMV8A 492 select BR2_ARCH_HAS_MMU_OPTIONAL 493 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 494config BR2_cortex_a75_a55 495 bool "cortex-A75/A55 big.LITTLE" 496 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 497 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 498 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 499 select BR2_ARM_CPU_HAS_FP_ARMV8 500 select BR2_ARM_CPU_ARMV8A 501 select BR2_ARCH_HAS_MMU_OPTIONAL 502 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 503config BR2_cortex_a76 504 bool "cortex-A76" 505 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 506 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 507 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 508 select BR2_ARM_CPU_HAS_FP_ARMV8 509 select BR2_ARM_CPU_ARMV8A 510 select BR2_ARCH_HAS_MMU_OPTIONAL 511 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 512config BR2_cortex_a76_a55 513 bool "cortex-A76/A55 big.LITTLE" 514 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 515 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 516 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 517 select BR2_ARM_CPU_HAS_FP_ARMV8 518 select BR2_ARM_CPU_ARMV8A 519 select BR2_ARCH_HAS_MMU_OPTIONAL 520 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 521config BR2_neoverse_n1 522 bool "neoverse-N1 (aka ares)" 523 select BR2_ARM_CPU_HAS_ARM if !BR2_ARCH_IS_64 524 select BR2_ARM_CPU_HAS_NEON if !BR2_ARCH_IS_64 525 select BR2_ARM_CPU_HAS_THUMB2 if !BR2_ARCH_IS_64 526 select BR2_ARM_CPU_HAS_FP_ARMV8 527 select BR2_ARM_CPU_ARMV8A 528 select BR2_ARCH_HAS_MMU_OPTIONAL 529 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 530config BR2_tsv110 531 bool "tsv110" 532 depends on BR2_ARCH_IS_64 533 select BR2_ARM_CPU_HAS_FP_ARMV8 534 select BR2_ARM_CPU_ARMV8A 535 select BR2_ARCH_HAS_MMU_OPTIONAL 536 select BR2_ARCH_NEEDS_GCC_AT_LEAST_9 537 538comment "armv8.4a cores" 539config BR2_saphira 540 bool "saphira" 541 depends on BR2_ARCH_IS_64 542 select BR2_ARM_CPU_HAS_FP_ARMV8 543 select BR2_ARM_CPU_ARMV8A 544 select BR2_ARCH_HAS_MMU_OPTIONAL 545 select BR2_ARCH_NEEDS_GCC_AT_LEAST_8 546endchoice 547 548config BR2_ARM_ENABLE_NEON 549 bool "Enable NEON SIMD extension support" 550 depends on BR2_ARM_CPU_MAYBE_HAS_NEON 551 select BR2_ARM_CPU_HAS_NEON 552 help 553 For some CPU cores, the NEON SIMD extension is optional. 554 Select this option if you are certain your particular 555 implementation has NEON support and you want to use it. 556 557config BR2_ARM_ENABLE_VFP 558 bool "Enable VFP extension support" 559 depends on BR2_ARM_CPU_MAYBE_HAS_FPU 560 select BR2_ARM_CPU_HAS_FPV5 if BR2_ARM_CPU_MAYBE_HAS_FPV5 561 select BR2_ARM_CPU_HAS_FPV4 if BR2_ARM_CPU_MAYBE_HAS_FPV4 562 select BR2_ARM_CPU_HAS_VFPV4 if BR2_ARM_CPU_MAYBE_HAS_VFPV4 563 select BR2_ARM_CPU_HAS_VFPV3 if BR2_ARM_CPU_MAYBE_HAS_VFPV3 564 select BR2_ARM_CPU_HAS_VFPV2 if BR2_ARM_CPU_MAYBE_HAS_VFPV2 565 help 566 For some CPU cores, the VFP extension is optional. Select 567 this option if you are certain your particular 568 implementation has VFP support and you want to use it. 569 570choice 571 prompt "Target ABI" 572 default BR2_ARM_EABIHF if BR2_ARM_CPU_HAS_FPU 573 default BR2_ARM_EABI 574 depends on BR2_arm || BR2_armeb 575 help 576 Application Binary Interface to use. The Application Binary 577 Interface describes the calling conventions (how arguments 578 are passed to functions, how the return value is passed, how 579 system calls are made, etc.). 580 581config BR2_ARM_EABI 582 bool "EABI" 583 help 584 The EABI is currently the standard ARM ABI, which is used in 585 most projects. It supports both the 'soft' floating point 586 model (in which floating point instructions are emulated in 587 software) and the 'softfp' floating point model (in which 588 floating point instructions are executed using an hardware 589 floating point unit, but floating point arguments to 590 functions are passed in integer registers). 591 592 The 'softfp' floating point model is link-compatible with 593 the 'soft' floating point model, i.e you can link a library 594 built 'soft' with some other code built 'softfp'. 595 596 However, passing the floating point arguments in integer 597 registers is a bit inefficient, so if your ARM processor has 598 a floating point unit, and you don't have pre-compiled 599 'soft' or 'softfp' code, using the EABIhf ABI will provide 600 better floating point performances. 601 602 If your processor does not have a floating point unit, then 603 you must use this ABI. 604 605config BR2_ARM_EABIHF 606 bool "EABIhf" 607 depends on BR2_ARM_CPU_HAS_FPU 608 help 609 The EABIhf is an extension of EABI which supports the 'hard' 610 floating point model. This model uses the floating point 611 unit to execute floating point instructions, and passes 612 floating point arguments in floating point registers. 613 614 It is more efficient than EABI for floating point related 615 workload. However, it does not allow to link against code 616 that has been pre-built for the 'soft' or 'softfp' floating 617 point models. 618 619 If your processor has a floating point unit, and you don't 620 depend on existing pre-compiled code, this option is most 621 likely the best choice. 622 623endchoice 624 625choice 626 prompt "Floating point strategy" 627 default BR2_ARM_FPU_AUTO 628 default BR2_ARM_FPU_NEON_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8 && BR2_ARM_CPU_HAS_NEON 629 default BR2_ARM_FPU_NEON_VFPV4 if BR2_ARM_CPU_HAS_VFPV4 && BR2_ARM_CPU_HAS_NEON 630 default BR2_ARM_FPU_FP_ARMV8 if BR2_ARM_CPU_HAS_FP_ARMV8 631 default BR2_ARM_FPU_FPV5D16 if BR2_ARM_CPU_HAS_FPV5 632 default BR2_ARM_FPU_FPV4D16 if BR2_ARM_CPU_HAS_FPV4 633 default BR2_ARM_FPU_VFPV4D16 if BR2_ARM_CPU_HAS_VFPV4 634 default BR2_ARM_FPU_VFPV3D16 if BR2_ARM_CPU_HAS_VFPV3 635 default BR2_ARM_FPU_VFPV2 if BR2_ARM_CPU_HAS_VFPV2 636 default BR2_ARM_SOFT_FLOAT if !BR2_ARM_CPU_HAS_FPU 637 638config BR2_ARM_SOFT_FLOAT 639 bool "Soft float" 640 depends on BR2_ARM_EABI 641 select BR2_SOFT_FLOAT 642 help 643 This option allows to use software emulated floating 644 point. It should be used for ARM cores that do not include a 645 Vector Floating Point unit, such as ARMv5 cores (ARM926 for 646 example) or certain ARMv6 cores. 647 648config BR2_ARM_FPU_AUTO 649 bool "Auto" 650 help 651 This option allows to use GCC's default floating point unit. 652 653config BR2_ARM_FPU_VFPV2 654 bool "VFPv2" 655 depends on BR2_ARM_CPU_HAS_VFPV2 656 help 657 This option allows to use the VFPv2 floating point unit, as 658 available in some ARMv5 processors (ARM926EJ-S) and some 659 ARMv6 processors (ARM1136JF-S, ARM1176JZF-S and ARM11 660 MPCore). 661 662 Note that this option is also safe to use for newer cores 663 such as Cortex-A, because the VFPv3 and VFPv4 units are 664 backward compatible with VFPv2. 665 666config BR2_ARM_FPU_VFPV3 667 bool "VFPv3" 668 depends on BR2_ARM_CPU_HAS_VFPV3 669 help 670 This option allows to use the VFPv3 floating point unit, as 671 available in some ARMv7 processors (Cortex-A{8, 9}). This 672 option requires a VFPv3 unit that has 32 double-precision 673 registers, which is not necessarily the case in all SOCs 674 based on Cortex-A{8, 9}. If you're unsure, use VFPv3-D16 675 instead, which is guaranteed to work on all Cortex-A{8, 9}. 676 677 Note that this option is also safe to use for newer cores 678 that have a VFPv4 unit, because VFPv4 is backward compatible 679 with VFPv3. They must of course also have 32 680 double-precision registers. 681 682config BR2_ARM_FPU_VFPV3D16 683 bool "VFPv3-D16" 684 depends on BR2_ARM_CPU_HAS_VFPV3 685 help 686 This option allows to use the VFPv3 floating point unit, as 687 available in some ARMv7 processors (Cortex-A{8, 9}). This 688 option requires a VFPv3 unit that has 16 double-precision 689 registers, which is generally the case in all SOCs based on 690 Cortex-A{8, 9}, even though VFPv3 is technically optional on 691 Cortex-A9. This is the safest option for those cores. 692 693 Note that this option is also safe to use for newer cores 694 such that have a VFPv4 unit, because the VFPv4 is backward 695 compatible with VFPv3. 696 697config BR2_ARM_FPU_VFPV4 698 bool "VFPv4" 699 depends on BR2_ARM_CPU_HAS_VFPV4 700 help 701 This option allows to use the VFPv4 floating point unit, as 702 available in some ARMv7 processors (Cortex-A{5, 7, 12, 703 15}). This option requires a VFPv4 unit that has 32 704 double-precision registers, which is not necessarily the 705 case in all SOCs based on Cortex-A{5, 7, 12, 15}. If you're 706 unsure, you should probably use VFPv4-D16 instead. 707 708 Note that if you want binary code that works on all ARMv7 709 cores, including the earlier Cortex-A{8, 9}, you should 710 instead select VFPv3. 711 712config BR2_ARM_FPU_VFPV4D16 713 bool "VFPv4-D16" 714 depends on BR2_ARM_CPU_HAS_VFPV4 715 help 716 This option allows to use the VFPv4 floating point unit, as 717 available in some ARMv7 processors (Cortex-A{5, 7, 12, 718 15}). This option requires a VFPv4 unit that has 16 719 double-precision registers, which is always available on 720 Cortex-A12 and Cortex-A15, but optional on Cortex-A5 and 721 Cortex-A7. 722 723 Note that if you want binary code that works on all ARMv7 724 cores, including the earlier Cortex-A{8, 9}, you should 725 instead select VFPv3-D16. 726 727config BR2_ARM_FPU_NEON 728 bool "NEON" 729 depends on BR2_ARM_CPU_HAS_NEON 730 help 731 This option allows to use the NEON SIMD unit, as available 732 in some ARMv7 processors, as a floating-point unit. It 733 should however be noted that using NEON for floating point 734 operations doesn't provide a complete compatibility with the 735 IEEE 754. 736 737config BR2_ARM_FPU_NEON_VFPV4 738 bool "NEON/VFPv4" 739 depends on BR2_ARM_CPU_HAS_VFPV4 740 depends on BR2_ARM_CPU_HAS_NEON 741 help 742 This option allows to use both the VFPv4 and the NEON SIMD 743 units for floating point operations. Note that some ARMv7 744 cores do not necessarily have VFPv4 and/or NEON support, for 745 example on Cortex-A5 and Cortex-A7, support for VFPv4 and 746 NEON is optional. 747 748config BR2_ARM_FPU_FPV4D16 749 bool "FPv4-D16" 750 depends on BR2_ARM_CPU_HAS_FPV4 751 help 752 This option allows to use the FPv4-SP (single precision) 753 floating point unit, as available in some ARMv7m processors 754 (Cortex-M4). 755 756config BR2_ARM_FPU_FPV5D16 757 bool "FPv5-D16" 758 depends on BR2_ARM_CPU_HAS_FPV5 759 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 760 help 761 This option allows to use the FPv5-SP (single precision) 762 floating point unit, as available in some ARMv7m processors 763 (Cortex-M7). 764 765 Note that if you want binary code that works on the earlier 766 Cortex-M4, you should instead select FPv4-D16. 767 768config BR2_ARM_FPU_FPV5DPD16 769 bool "FPv5-DP-D16" 770 depends on BR2_ARM_CPU_HAS_FPV5 771 select BR2_ARCH_NEEDS_GCC_AT_LEAST_5 772 help 773 This option allows to use the FPv5-DP (double precision) 774 floating point unit, as available in some ARMv7m processors 775 (Cortex-M7). 776 777 Note that if you want binary code that works on the earlier 778 Cortex-M4, you should instead select FPv4-D16. 779 780config BR2_ARM_FPU_FP_ARMV8 781 bool "FP-ARMv8" 782 depends on BR2_ARM_CPU_HAS_FP_ARMV8 783 help 784 This option allows to use the ARMv8 floating point unit. 785 786config BR2_ARM_FPU_NEON_FP_ARMV8 787 bool "NEON/FP-ARMv8" 788 depends on BR2_ARM_CPU_HAS_FP_ARMV8 789 depends on BR2_ARM_CPU_HAS_NEON 790 help 791 This option allows to use both the ARMv8 floating point unit 792 and the NEON SIMD unit for floating point operations. 793 794endchoice 795 796choice 797 prompt "ARM instruction set" 798 depends on BR2_arm || BR2_armeb 799 800config BR2_ARM_INSTRUCTIONS_ARM 801 bool "ARM" 802 depends on BR2_ARM_CPU_HAS_ARM 803 help 804 This option instructs the compiler to generate regular ARM 805 instructions, that are all 32 bits wide. 806 807config BR2_ARM_INSTRUCTIONS_THUMB 808 bool "Thumb" 809 depends on BR2_ARM_CPU_HAS_THUMB 810 # Thumb-1 and VFP are not compatible 811 depends on BR2_ARM_SOFT_FLOAT 812 help 813 This option instructions the compiler to generate Thumb 814 instructions, which allows to mix 16 bits instructions and 815 32 bits instructions. This generally provides a much smaller 816 compiled binary size. 817 818comment "Thumb1 is not compatible with VFP" 819 depends on BR2_ARM_CPU_HAS_THUMB 820 depends on !BR2_ARM_SOFT_FLOAT 821 822config BR2_ARM_INSTRUCTIONS_THUMB2 823 bool "Thumb2" 824 depends on BR2_ARM_CPU_HAS_THUMB2 825 help 826 This option instructions the compiler to generate Thumb2 827 instructions, which allows to mix 16 bits instructions and 828 32 bits instructions. This generally provides a much smaller 829 compiled binary size. 830 831endchoice 832 833config BR2_ARCH 834 default "arm" if BR2_arm 835 default "armeb" if BR2_armeb 836 default "aarch64" if BR2_aarch64 837 default "aarch64_be" if BR2_aarch64_be 838 839config BR2_NORMALIZED_ARCH 840 default "arm" if BR2_arm || BR2_armeb 841 default "arm64" if BR2_aarch64 || BR2_aarch64_be 842 843config BR2_ENDIAN 844 default "LITTLE" if (BR2_arm || BR2_aarch64) 845 default "BIG" if (BR2_armeb || BR2_aarch64_be) 846 847config BR2_GCC_TARGET_CPU 848 # armv4 849 default "arm920t" if BR2_arm920t 850 default "arm922t" if BR2_arm922t 851 default "fa526" if BR2_fa526 852 default "strongarm" if BR2_strongarm 853 # armv5 854 default "arm926ej-s" if BR2_arm926t 855 default "iwmmxt" if BR2_iwmmxt 856 default "xscale" if BR2_xscale 857 # armv6 858 default "arm1136j-s" if BR2_arm1136j_s 859 default "arm1136jf-s" if BR2_arm1136jf_s 860 default "arm1176jz-s" if BR2_arm1176jz_s 861 default "arm1176jzf-s" if BR2_arm1176jzf_s 862 default "mpcore" if BR2_arm11mpcore && BR2_ARM_CPU_HAS_VFPV2 863 default "mpcorenovfp" if BR2_arm11mpcore 864 # armv7a 865 default "cortex-a5" if BR2_cortex_a5 866 default "cortex-a7" if BR2_cortex_a7 867 default "cortex-a8" if BR2_cortex_a8 868 default "cortex-a9" if BR2_cortex_a9 869 default "cortex-a12" if BR2_cortex_a12 870 default "cortex-a15" if BR2_cortex_a15 871 default "cortex-a15.cortex-a7" if BR2_cortex_a15_a7 872 default "cortex-a17" if BR2_cortex_a17 873 default "cortex-a17.cortex-a7" if BR2_cortex_a17_a7 874 default "marvell-pj4" if BR2_pj4 875 # armv7m 876 default "cortex-m3" if BR2_cortex_m3 877 default "cortex-m4" if BR2_cortex_m4 878 default "cortex-m7" if BR2_cortex_m7 879 # armv8a 880 default "cortex-a32" if BR2_cortex_a32 881 default "cortex-a35" if BR2_cortex_a35 882 default "cortex-a53" if BR2_cortex_a53 883 default "cortex-a57" if BR2_cortex_a57 884 default "cortex-a57.cortex-a53" if BR2_cortex_a57_a53 885 default "cortex-a72" if BR2_cortex_a72 886 default "cortex-a72.cortex-a53" if BR2_cortex_a72_a53 887 default "cortex-a73" if BR2_cortex_a73 888 default "cortex-a73.cortex-a35" if BR2_cortex_a73_a35 889 default "cortex-a73.cortex-a53" if BR2_cortex_a73_a53 890 default "emag" if BR2_emag 891 default "exynos-m1" if BR2_exynos_m1 892 default "falkor" if BR2_falkor 893 default "phecda" if BR2_phecda 894 default "qdf24xx" if BR2_qdf24xx 895 default "thunderx" if BR2_thunderx && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 896 default "octeontx" if BR2_thunderx && BR2_TOOLCHAIN_GCC_AT_LEAST_9 897 default "thunderxt81" if BR2_thunderxt81 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 898 default "octeontx81" if BR2_thunderxt81 && BR2_TOOLCHAIN_GCC_AT_LEAST_9 899 default "thunderxt83" if BR2_thunderxt83 && !BR2_TOOLCHAIN_GCC_AT_LEAST_9 900 default "octeontx83" if BR2_thunderxt83 && BR2_TOOLCHAIN_GCC_AT_LEAST_9 901 default "thunderxt88" if BR2_thunderxt88 902 default "thunderxt88p1" if BR2_thunderxt88p1 903 default "xgene1" if BR2_xgene1 904 # armv8.1a 905 default "thunderx2t99" if BR2_thunderx2t99 906 default "thunderx2t99p1" if BR2_thunderx2t99p1 907 default "vulcan" if BR2_vulcan 908 # armv8.2a 909 default "cortex-a55" if BR2_cortex_a55 910 default "cortex-a75" if BR2_cortex_a75 911 default "cortex-a75.cortex-a55" if BR2_cortex_a75_a55 912 default "cortex-a76" if BR2_cortex_a76 913 default "cortex-a76.cortex-a55" if BR2_cortex_a76_a55 914 default "neoverse-n1" if BR2_neoverse_n1 915 default "tsv110" if BR2_tsv110 916 # armv8.4a 917 default "saphira" if BR2_saphira 918 919config BR2_GCC_TARGET_ABI 920 default "aapcs-linux" if BR2_arm || BR2_armeb 921 default "lp64" if BR2_aarch64 || BR2_aarch64_be 922 923config BR2_GCC_TARGET_FPU 924 default "" if BR2_ARM_FPU_AUTO 925 default "vfp" if BR2_ARM_FPU_VFPV2 926 default "vfpv3" if BR2_ARM_FPU_VFPV3 927 default "vfpv3-d16" if BR2_ARM_FPU_VFPV3D16 928 default "vfpv4" if BR2_ARM_FPU_VFPV4 929 default "vfpv4-d16" if BR2_ARM_FPU_VFPV4D16 930 default "neon" if BR2_ARM_FPU_NEON 931 default "neon-vfpv4" if BR2_ARM_FPU_NEON_VFPV4 932 default "fpv4-sp-d16" if BR2_ARM_FPU_FPV4D16 933 default "fpv5-sp-d16" if BR2_ARM_FPU_FPV5D16 934 default "fpv5-d16" if BR2_ARM_FPU_FPV5DPD16 935 default "fp-armv8" if BR2_ARM_FPU_FP_ARMV8 936 default "neon-fp-armv8" if BR2_ARM_FPU_NEON_FP_ARMV8 937 depends on BR2_arm || BR2_armeb 938 939config BR2_GCC_TARGET_FLOAT_ABI 940 default "soft" if BR2_ARM_SOFT_FLOAT 941 default "softfp" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABI 942 default "hard" if !BR2_ARM_SOFT_FLOAT && BR2_ARM_EABIHF 943 944config BR2_GCC_TARGET_MODE 945 default "arm" if BR2_ARM_INSTRUCTIONS_ARM 946 default "thumb" if BR2_ARM_INSTRUCTIONS_THUMB || BR2_ARM_INSTRUCTIONS_THUMB2 947 948config BR2_READELF_ARCH_NAME 949 default "ARM" if BR2_arm || BR2_armeb 950 default "AArch64" if BR2_aarch64 || BR2_aarch64_be 951 952# vim: ft=kconfig 953# -*- mode:kconfig; -*- 954