Home
last modified time | relevance | path

Searched +full:60 +full:mhz (Results 1 – 25 of 1007) sorted by relevance

12345678910>>...41

/OK3568_Linux_fs/kernel/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
28 mode "640x480-60"
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
[all …]
H A Dmatroxfb.rst294 maxclk:X maximum dotclock. X can be specified in MHz, kHz or Hz. Default is
299 70 for modes derived from `vesa` with yres <= 400, 60Hz for
327 - 83 MHz on G200
328 - 66 MHz on Millennium I
329 - 60 MHz on Millennium II
335 - my Millennium G200 oscillator has frequency range from 35 MHz to 380 MHz
336 (and it works with 8bpp on about 320 MHz dotclocks (and changed mclk)).
337 But Matrox says on product sheet that VCO limit is 50-250 MHz, so I believe
364 It is time to redraw whole screen 1000 times in 1024x768, 60Hz. It is
369 faster, it is kernel-space only time on P-II/350 MHz, Millennium I in 33 MHz
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/OK3568_Linux_fs/kernel/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
37 "mac2", 60, 512, 384, 63828, 80, 16, 19, 1, 32, 3,
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
41 "mac5", 60, 640, 480, 39722, 32, 32, 33, 10, 96, 2,
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
57 "mac10", 60, 800, 600, 25000, 72, 56, 23, 1, 128, 4,
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
[all …]
H A Dvalkyriefb.h79 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
102 { 11, 28, 3 }, /* pixel clock = 79.55MHz for V=74.50Hz */
108 /* This used to be 12, 30, 3 for pixel clock = 78.12MHz for V=72.12Hz, but
118 { 12, 29, 3 }, /* pixel clock = 75.52MHz for V=69.71Hz? */
126 /* Register values for 1024x768, 60Hz mode (14) */
129 { 15, 31, 3 }, /* pixel clock = 64.58MHz for V=59.62Hz */
138 { 23, 42, 3 }, /* pixel clock = 57.07MHz for V=74.27Hz */
146 { 17, 27, 3 }, /* pixel clock = 49.63MHz for V=71.66Hz */
151 /* Register values for 800x600, 60Hz mode (10) */
154 { 25, 32, 3 }, /* pixel clock = 40.0015MHz,
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.h45 #define FRA_ERR_20MHZ 60
80 /* Index for first 20MHz OFDM SISO rate */
82 /* Index for first 20MHz OFDM CDD rate */
84 /* Index for first 40MHz OFDM SISO rate */
86 /* Index for first 40MHz OFDM CDD rate */
87 #define WL_TX_POWER_OFDM40_CDD_FIRST 60
89 /* Index for first 20MHz MCS SISO rate */
91 /* Index for first 20MHz MCS CDD rate */
93 /* Index for first 20MHz MCS STBC rate */
95 /* Index for first 20MHz MCS SDM rate */
[all …]
/OK3568_Linux_fs/kernel/drivers/net/wireless/mediatek/mt76/
H A Dmt76x02_dfs.c29 /* 20MHz */
34 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
38 /* 40MHz */
43 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
47 /* 80MHz */
52 RADAR_SPEC(3, 60, 20, 46, 300, 640, 80, 4900, 10100, 80, 0,
59 /* 20MHz */
66 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
68 /* 40MHz */
75 RADAR_SPEC(2, 60, 15, 63, 640, 2080, 32, 19600, 40200, 32, 0,
[all …]
/OK3568_Linux_fs/kernel/arch/powerpc/boot/
H A Dutil.S22 * timebase in nanoseconds. This used to be hardcoded to be 60ns
23 * (period of 66MHz/4). Now a variable is used that is initialized to
24 * 60 for backward compatibility, but it can be overridden as necessary
32 .long 60
43 * timebase_period_ns defaults to 60 (16.6MHz) */
/OK3568_Linux_fs/external/xserver/hw/xfree86/common/
H A Dextramodes10 # 1400x1050 @ 60Hz (VESA GTF) hsync: 65.5kHz
19 # 2048x1536 @ 60Hz (VESA GTF) hsync: 95.3kHz
30 # 640x360 59.32 Hz (CVT 0.23M9-R) hsync: 22.19 kHz; pclk: 17.75 MHz
33 # 640x360 59.84 Hz (CVT 0.23M9) hsync: 22.50 kHz; pclk: 18.00 MHz
36 # 720x405 58.99 Hz (CVT 0.29M9-R) hsync: 24.72 kHz; pclk: 21.75 MHz
39 # 720x405 59.51 Hz (CVT 0.29M9) hsync: 25.11 kHz; pclk: 22.50 MHz
42 # 864x486 59.57 Hz (CVT 0.42M9-R) hsync: 29.79 kHz; pclk: 30.50 MHz
45 # 864x486 59.92 Hz (CVT 0.42M9) hsync: 30.32 kHz; pclk: 32.50 MHz
48 # 960x540 59.82 Hz (CVT 0.52M9-R) hsync: 33.26 kHz; pclk: 37.25 MHz
51 # 960x540 59.63 Hz (CVT 0.52M9) hsync: 33.51 kHz; pclk: 40.75 MHz
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/usb/
H A Dqcom,dwc3.yaml48 - description: Master/Core clock, has to be >= 125 MHz
49 for SS operation and >= 60MHz for HS operation.
52 in host mode. Its frequency should be 19.2MHz.
71 - description: Must be 19.2MHz (19200000).
72 - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
/OK3568_Linux_fs/kernel/Documentation/userspace-api/media/v4l/
H A Dvidioc-enumstd.rst136 ``V4L2_STD_PAL_60`` is a hybrid standard with 525 lines, 60 Hz refresh
137 rate, and PAL color modulation with a 4.43 MHz color subcarrier. Some
139 a 50/60 Hz agnostic PAL TV.
147 ``V4L2_STD_NTSC_443`` is a hybrid standard with 525 lines, 60 Hz refresh
148 rate, and NTSC color modulation with a 4.43 MHz color subcarrier.
268 * - Nominal radio-frequency channel bandwidth (MHz)
280 * - Sound carrier relative to vision carrier (MHz)
331 New Zealand uses a sound carrier displaced 5.4996 ± 0.0005 MHz from
337 is being introduced. The second carrier is 5.85 MHz above the vision
343 second sound carrier is 6.552 MHz above the vision carrier and is
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852be/phl/
H A Drtw_general_def.h389 RTW_USB_SPEED_HIGH = 2, /*U2 (2.0)- 2.1 - 480 Mbps - 60MBs*/
439 * RU106 : 53 54 55 56 57 58 59 60
446 /* 20MHz - 1 */
456 /* 20MHz - 2 */
468 /* 20MHz - 3 */
478 /* 20MHz - 4 */
488 /* 20MHz - 1 */
493 /* 20MHz - 2 */
498 /* 20MHz - 3 */
503 /* 20MHz - 4 */
[all …]
/OK3568_Linux_fs/external/rkwifibt/drivers/rtl8852bs/phl/
H A Drtw_general_def.h389 RTW_USB_SPEED_HIGH = 2, /*U2 (2.0)- 2.1 - 480 Mbps - 60MBs*/
439 * RU106 : 53 54 55 56 57 58 59 60
446 /* 20MHz - 1 */
456 /* 20MHz - 2 */
468 /* 20MHz - 3 */
478 /* 20MHz - 4 */
488 /* 20MHz - 1 */
493 /* 20MHz - 2 */
498 /* 20MHz - 3 */
503 /* 20MHz - 4 */
[all …]
/OK3568_Linux_fs/u-boot/include/configs/
H A Domap3_cairo.h99 "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
100 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
101 "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
102 "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
103 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
104 "mw 60 09 00 1; i2c mw 60 06 10 1\0" \
105 "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
106 "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
107 "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
108 "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
[all …]
/OK3568_Linux_fs/u-boot/doc/
H A DREADME.m54418twr118 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
119 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
120 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
121 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
122 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
123 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
134 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
135 INP CLK 50 MHz VCO CLK 500 MHz
151 ethaddr=00:e0:0c:bc:e5:60
181 cpufreq = 250 MHz
[all …]
/OK3568_Linux_fs/u-boot/board/armadeus/apf27/
H A Dapf27.h28 * ACFG_CLK_FREQ (2/3 MPLL clock or ext 266 MHZ)
30 #define ACFG_MPCTL0_VAL 0x01EF15D5 /* 399.000 MHz */
34 #define ACFG_CLK_FREQ (CONFIG_MPLL_FREQ*2/3) /* 266 MHz */
37 #define ACFG_SPCTL0_VAL 0x0475206F /* 299.99937 MHz */
39 #define CONFIG_SPLL_FREQ 300 /* MHz */
42 #define CONFIG_ARM_FREQ 399 /* up to 400 MHz */
47 #define CONFIG_PERIF1_FREQ 16 /* 16.625 MHz UART, GPT, PWM */
48 #define CONFIG_PERIF2_FREQ 33 /* 33.25 MHz CSPI and SDHC */
49 #define CONFIG_PERIF3_FREQ 33 /* 33.25 MHz LCD */
50 #define CONFIG_PERIF4_FREQ 33 /* 33.25 MHz CSI */
[all …]
/OK3568_Linux_fs/kernel/drivers/staging/vt6655/
H A Drf.c57 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */
58 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */
59 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */
60 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */
61 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */
62 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */
63 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */
64 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */
65 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */
66 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */
[all …]
/OK3568_Linux_fs/rkbin/tools/
H A Dddrbin_tool_user_guide.txt159 ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz.
160 lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz.
161 ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz.
162 lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz.
163 ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz.
164 lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz.
165 lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz.
166 lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz.
171 | platform | support frequencies(MHZ) |
202 | RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] |
[all …]
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-of-arasan.c50 #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
53 #define VERSAL_OCLK_PHASE {0, 60, 48, 0, 48, 72, 90, 36, 60, 90, 0}
165 * met at 25MHz for Default Speed mode, those controllers work at
166 * 19MHz instead
308 * requirements met at 25MHz for Default Speed mode, in sdhci_arasan_set_clock()
309 * those controllers work at 19MHz instead. in sdhci_arasan_set_clock()
645 /* For 50MHz clock, 30 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
649 /* For 100MHz clock, 15 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
654 /* For 200MHz clock, 8 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
713 /* For 50MHz clock, 120 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
[all …]
/OK3568_Linux_fs/external/xserver/debian/patches/
H A D001_fedora_extramodes.patch18 +# 1152x864 @ 60.00 Hz (GTF) hsync: 53.70 kHz; pclk: 81.62 MHz
21 +# 1152x864 @ 70.00 Hz (GTF) hsync: 63.00 kHz; pclk: 96.77 MHz
24 +# 1152x864 @ 75.00 Hz (GTF) hsync: 67.65 kHz; pclk: 104.99 MHz
27 +# 1152x864 @ 85.00 Hz (GTF) hsync: 77.10 kHz; pclk: 119.65 MHz
33 +# 1152x864 @ 100.00 Hz (GTF) hsync: 91.50 kHz; pclk: 143.47 MHz
36 +# 1360x768 59.96 Hz (CVT) hsync: 47.37 kHz; pclk: 72.00 MHz
39 +# 1360x768 59.80 Hz (CVT) hsync: 47.72 kHz; pclk: 84.75 MHz
42 # 1400x1050 @ 60Hz (VESA GTF) hsync: 65.5kHz
45 +# 1400x1050 @ 70.00 Hz (GTF) hsync: 76.51 kHz; pclk: 145.06 MHz
51 +# 1400x1050 @ 85.00 Hz (GTF) hsync: 93.76 kHz; pclk: 179.26 MHz
[all …]
/OK3568_Linux_fs/kernel/Documentation/admin-guide/media/
H A Dvivid.rst325 framerate of 59.94 Hz is really different from 60 Hz. If the framerate
335 supports frames per second settings of 10, 15, 25, 30, 50 and 60 fps. Which ones
359 is the newest in time. For 60 Hz standards that is reversed: the bottom field
363 contain the top field for 50 Hz standards and the bottom field for 60 Hz
378 The TV 'tuner' supports a frequency range of 44-958 MHz. Channels are available
379 every 6 MHz, starting from 49.25 MHz. For each channel the generated image
380 will be in color for the +/- 0.25 MHz around it, and in grayscale for
381 +/- 1 MHz around the channel. Beyond that it is just noise. The VIDIOC_G_TUNER
382 ioctl will return 100% signal strength for +/- 0.25 MHz and 50% for +/- 1 MHz.
386 The audio subchannels that are returned are MONO for the +/- 1 MHz range around
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/
H A Dmax8952.txt15 - 0: 26 MHz
16 - 1: 13 MHz
17 - 2: 19.2 MHz
18 Defaults to 26 MHz if not specified.
33 vdd_arm_reg: pmic@60 {
/OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/
H A Dcx24110.c49 {0x06,0xa5}, /* @ PLL 60MHz */
50 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
244 /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz, in cx24110_set_symbolrate()
248 if(srate<90999000UL/4) { /* sample rate 45MHz*/ in cx24110_set_symbolrate()
252 } else if(srate<60666000UL/2) { /* sample rate 60MHz */ in cx24110_set_symbolrate()
256 } else if(srate<80888000UL/2) { /* sample rate 80MHz */ in cx24110_set_symbolrate()
260 } else { /* sample rate 90MHz */ in cx24110_set_symbolrate()
549 /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz. in cx24110_get_frontend()
619 .frequency_min_hz = 950 * MHz,
620 .frequency_max_hz = 2150 * MHz,
/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmem.h111 /* Hynix part of Overo (165MHz optimized) 6.06ns */
137 /* Hynix part of AM/DM37xEVM (200MHz optimized) */
163 /* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
171 #define INFINEON_TRC_165 10 /* 60/6 = 10 */
189 /* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
197 #define MICRON_TRC_165 10 /* 60/6 = 10 */
226 /* Micron part (200MHz optimized) 5 ns */
252 /* Samsung K4X51163PG - FGC6 (165MHz optimized) 6.06ns - from 2010.90 src */
295 /* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
303 #define NUMONYX_TRC_165 10 /* 60/6 = 10 */
[all …]
/OK3568_Linux_fs/kernel/drivers/usb/gadget/udc/
H A Dfsl_mxc_udc.c59 /* make sure USB_CLK is running at 60 MHz +/- 1000 Hz */ in fsl_udc_clk_init()
64 dev_err(&pdev->dev, "USB_CLK=%lu, should be 60MHz\n", freq); in fsl_udc_clk_init()

12345678910>>...41