1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Configuration settings for the QUIPOS Cairo board. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) DENX GmbH 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Author : 7*4882a593Smuzhiyun * Albert ARIBAUD <albert.aribaud@3adev.fr> 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Derived from EVM code by 10*4882a593Smuzhiyun * Manikandan Pillai <mani.pillai@ti.com> 11*4882a593Smuzhiyun * Itself derived from Beagle Board and 3430 SDP code by 12*4882a593Smuzhiyun * Richard Woodruff <r-woodruff2@ti.com> 13*4882a593Smuzhiyun * Syed Mohammed Khasim <khasim@ti.com> 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Also derived from include/configs/omap3_beagle.h 16*4882a593Smuzhiyun * 17*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 18*4882a593Smuzhiyun */ 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #ifndef __OMAP3_CAIRO_CONFIG_H 21*4882a593Smuzhiyun #define __OMAP3_CAIRO_CONFIG_H 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 27*4882a593Smuzhiyun * 64 bytes before this address should be set aside for u-boot.img's 28*4882a593Smuzhiyun * header. That is 0x800FFFC0--0x80100000 should not be used for any 29*4882a593Smuzhiyun * other needs. We use this rather than the inherited defines from 30*4882a593Smuzhiyun * ti_armv7_common.h for backwards compatibility. 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun #define CONFIG_SYS_TEXT_BASE 0x80100000 33*4882a593Smuzhiyun #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE 34*4882a593Smuzhiyun #define CONFIG_SPL_BSS_START_ADDR 0x80000000 35*4882a593Smuzhiyun #define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ 36*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 37*4882a593Smuzhiyun #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #include <configs/ti_omap3_common.h> 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define CONFIG_MISC_INIT_R 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define CONFIG_REVISION_TAG 1 44*4882a593Smuzhiyun #define CONFIG_ENV_OVERWRITE 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Enable Multi Bus support for I2C */ 47*4882a593Smuzhiyun #define CONFIG_I2C_MULTI_BUS 1 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Probe all devices */ 50*4882a593Smuzhiyun #define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* 53*4882a593Smuzhiyun * TWL4030 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun #define CONFIG_TWL4030_LED 1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * Board NAND Info. 59*4882a593Smuzhiyun */ 60*4882a593Smuzhiyun #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 61*4882a593Smuzhiyun /* devices */ 62*4882a593Smuzhiyun #define CONFIG_EXTRA_ENV_SETTINGS \ 63*4882a593Smuzhiyun "machid=ffffffff\0" \ 64*4882a593Smuzhiyun "fdt_high=0x87000000\0" \ 65*4882a593Smuzhiyun "baudrate=115200\0" \ 66*4882a593Smuzhiyun "fec_addr=00:50:C2:7E:90:F0\0" \ 67*4882a593Smuzhiyun "netmask=255.255.255.0\0" \ 68*4882a593Smuzhiyun "ipaddr=192.168.2.9\0" \ 69*4882a593Smuzhiyun "gateway=192.168.2.1\0" \ 70*4882a593Smuzhiyun "serverip=192.168.2.10\0" \ 71*4882a593Smuzhiyun "nfshost=192.168.2.10\0" \ 72*4882a593Smuzhiyun "stdin=serial\0" \ 73*4882a593Smuzhiyun "stdout=serial\0" \ 74*4882a593Smuzhiyun "stderr=serial\0" \ 75*4882a593Smuzhiyun "bootargs_mmc_ramdisk=mem=128M " \ 76*4882a593Smuzhiyun "console=ttyO1,115200n8 " \ 77*4882a593Smuzhiyun "root=/dev/ram0 rw " \ 78*4882a593Smuzhiyun "initrd=0x81600000,16M " \ 79*4882a593Smuzhiyun "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ 80*4882a593Smuzhiyun "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ 81*4882a593Smuzhiyun "mmcboot=mmc init; " \ 82*4882a593Smuzhiyun "fatload mmc 0 0x80000000 uImage; " \ 83*4882a593Smuzhiyun "fatload mmc 0 0x81600000 ramdisk.gz; " \ 84*4882a593Smuzhiyun "setenv bootargs ${bootargs_mmc_ramdisk}; " \ 85*4882a593Smuzhiyun "bootm 0x80000000\0" \ 86*4882a593Smuzhiyun "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ 87*4882a593Smuzhiyun "root=/dev/nfs " \ 88*4882a593Smuzhiyun "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ 89*4882a593Smuzhiyun "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ 90*4882a593Smuzhiyun "omap_vout.vid1_static_vrfb_alloc=y\0" \ 91*4882a593Smuzhiyun "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ 92*4882a593Smuzhiyun "bootm 0x80000000\0" \ 93*4882a593Smuzhiyun "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ 94*4882a593Smuzhiyun "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ 95*4882a593Smuzhiyun "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ 96*4882a593Smuzhiyun "omapfb.rotate_type=1\0" \ 97*4882a593Smuzhiyun "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ 98*4882a593Smuzhiyun "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ 99*4882a593Smuzhiyun "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 100*4882a593Smuzhiyun "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 101*4882a593Smuzhiyun "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ 102*4882a593Smuzhiyun "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 103*4882a593Smuzhiyun "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ 104*4882a593Smuzhiyun "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ 105*4882a593Smuzhiyun "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 106*4882a593Smuzhiyun "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 107*4882a593Smuzhiyun "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ 108*4882a593Smuzhiyun "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ 109*4882a593Smuzhiyun "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ 110*4882a593Smuzhiyun "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ 111*4882a593Smuzhiyun "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ 112*4882a593Smuzhiyun "nand erase 0 20000; " \ 113*4882a593Smuzhiyun "fatload mmc 0 0x81600000 MLO; " \ 114*4882a593Smuzhiyun "nandecc hw; " \ 115*4882a593Smuzhiyun "nand write.i 0x81600000 0 20000;\0" \ 116*4882a593Smuzhiyun "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ 117*4882a593Smuzhiyun "nand erase 80000 40000; " \ 118*4882a593Smuzhiyun "fatload mmc 0 0x81600000 u-boot.bin; " \ 119*4882a593Smuzhiyun "nandecc sw; " \ 120*4882a593Smuzhiyun "nand write.i 0x81600000 80000 40000;\0" \ 121*4882a593Smuzhiyun "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ 122*4882a593Smuzhiyun "nand erase 280000 300000; " \ 123*4882a593Smuzhiyun "fatload mmc 0 0x81600000 uImage; " \ 124*4882a593Smuzhiyun "nandecc sw; " \ 125*4882a593Smuzhiyun "nand write.i 0x81600000 280000 300000;\0" \ 126*4882a593Smuzhiyun "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ 127*4882a593Smuzhiyun "nandecc sw; " \ 128*4882a593Smuzhiyun "nand write.jffs2 0x680000 0xFF ${filesize}; " \ 129*4882a593Smuzhiyun "nand erase 680000 ${filesize}; " \ 130*4882a593Smuzhiyun "nand write.jffs2 81600000 680000 ${filesize};\0" \ 131*4882a593Smuzhiyun "flash_scrub=nand scrub; " \ 132*4882a593Smuzhiyun "run flash_xloader; " \ 133*4882a593Smuzhiyun "run flash_uboot; " \ 134*4882a593Smuzhiyun "run flash_kernel; " \ 135*4882a593Smuzhiyun "run flash_rootfs;\0" \ 136*4882a593Smuzhiyun "flash_all=run ledred; " \ 137*4882a593Smuzhiyun "nand erase.chip; " \ 138*4882a593Smuzhiyun "run ledorange; " \ 139*4882a593Smuzhiyun "run flash_xloader; " \ 140*4882a593Smuzhiyun "run flash_uboot; " \ 141*4882a593Smuzhiyun "run flash_kernel; " \ 142*4882a593Smuzhiyun "run flash_rootfs; " \ 143*4882a593Smuzhiyun "run ledgreen; " \ 144*4882a593Smuzhiyun "run boot_nand; \0" \ 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #define CONFIG_BOOTCOMMAND \ 147*4882a593Smuzhiyun "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ 148*4882a593Smuzhiyun "else run boot_nand; fi" 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* 151*4882a593Smuzhiyun * OMAP3 has 12 GP timers, they can be driven by the system clock 152*4882a593Smuzhiyun * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 153*4882a593Smuzhiyun * This rate is divided by a local divisor. 154*4882a593Smuzhiyun */ 155*4882a593Smuzhiyun #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /*----------------------------------------------------------------------- 158*4882a593Smuzhiyun * FLASH and environment organization 159*4882a593Smuzhiyun */ 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun /* **** PISMO SUPPORT *** */ 162*4882a593Smuzhiyun #if defined(CONFIG_CMD_NAND) 163*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_BASE NAND_BASE 164*4882a593Smuzhiyun #endif 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* Monitor at start of flash */ 167*4882a593Smuzhiyun #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 168*4882a593Smuzhiyun #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 171*4882a593Smuzhiyun #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ 172*4882a593Smuzhiyun #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 175*4882a593Smuzhiyun #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 176*4882a593Smuzhiyun #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun /* Defines for SPL */ 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* NAND boot config */ 181*4882a593Smuzhiyun #define CONFIG_SYS_NAND_5_ADDR_CYCLE 182*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_COUNT 64 183*4882a593Smuzhiyun #define CONFIG_SYS_NAND_PAGE_SIZE 2048 184*4882a593Smuzhiyun #define CONFIG_SYS_NAND_OOBSIZE 64 185*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 186*4882a593Smuzhiyun #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 187*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 188*4882a593Smuzhiyun 10, 11, 12, 13} 189*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCSIZE 512 190*4882a593Smuzhiyun #define CONFIG_SYS_NAND_ECCBYTES 3 191*4882a593Smuzhiyun #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 192*4882a593Smuzhiyun #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 193*4882a593Smuzhiyun /* NAND: SPL falcon mode configs */ 194*4882a593Smuzhiyun #ifdef CONFIG_SPL_OS_BOOT 195*4882a593Smuzhiyun #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 196*4882a593Smuzhiyun #endif 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* env defaults */ 199*4882a593Smuzhiyun #define CONFIG_BOOTFILE "uImage" 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun /* Override OMAP3 common serial console configuration from UART3 202*4882a593Smuzhiyun * to UART2. 203*4882a593Smuzhiyun * 204*4882a593Smuzhiyun * Attention: for UART2, special MUX settings (MUX_DEFAULT(), MCBSP3) 205*4882a593Smuzhiyun * are needed and peripheral clocks for UART2 must be enabled in 206*4882a593Smuzhiyun * function per_clocks_enable(). 207*4882a593Smuzhiyun */ 208*4882a593Smuzhiyun #undef CONFIG_CONS_INDEX 209*4882a593Smuzhiyun #define CONFIG_CONS_INDEX 2 210*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD 211*4882a593Smuzhiyun #undef CONFIG_SYS_NS16550_COM3 212*4882a593Smuzhiyun #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 213*4882a593Smuzhiyun #undef CONFIG_SERIAL3 214*4882a593Smuzhiyun #define CONFIG_SERIAL2 215*4882a593Smuzhiyun #endif 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* Provide the MACH_TYPE value the vendor kernel requires */ 218*4882a593Smuzhiyun #define CONFIG_MACH_TYPE 3063 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun /*----------------------------------------------------------------------- 221*4882a593Smuzhiyun * FLASH and environment organization 222*4882a593Smuzhiyun */ 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun /* **** PISMO SUPPORT *** */ 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 227*4882a593Smuzhiyun /* on one chip */ 228*4882a593Smuzhiyun #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun /*----------------------------------------------------------------------- 231*4882a593Smuzhiyun * CFI FLASH driver setup 232*4882a593Smuzhiyun */ 233*4882a593Smuzhiyun /* timeout values are in ticks */ 234*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 235*4882a593Smuzhiyun #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* Flash banks JFFS2 should use */ 238*4882a593Smuzhiyun #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 239*4882a593Smuzhiyun CONFIG_SYS_MAX_NAND_DEVICE) 240*4882a593Smuzhiyun #define CONFIG_SYS_JFFS2_MEM_NAND 241*4882a593Smuzhiyun /* use flash_info[2] */ 242*4882a593Smuzhiyun #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 243*4882a593Smuzhiyun #define CONFIG_SYS_JFFS2_NUM_BANKS 1 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun #endif /* __OMAP3_CAIRO_CONFIG_H */ 246